Search results for: chaotic circuit
Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 868

Search results for: chaotic circuit

808 PSRR Enhanced LDO Regulator Using Noise Sensing Circuit

Authors: Min-ju Kwon, Chae-won Kim, Jeong-yun Seo, Hee-guk Chae, Yong-seo Koo

Abstract:

In this paper, we presented the LDO (low-dropout) regulator which enhanced the PSRR by applying the constant current source generation technique through the BGR (Band Gap Reference) to form the noise sensing circuit. The current source through the BGR has a constant current value even if the applied voltage varies. Then, the noise sensing circuit, which is composed of the current source through the BGR, operated between the error amplifier and the pass transistor gate of the LDO regulator. As a result, the LDO regulator has a PSRR of -68.2 dB at 1k Hz, -45.85 dB at 1 MHz and -45 dB at 10 MHz. the other performance of the proposed LDO was maintained at the same level of the conventional LDO regulator.

Keywords: LDO regulator, noise sensing circuit, current reference, pass transistor

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807 Synchronization of Semiconductor Laser Networks

Authors: R. M. López-Gutiérrez, L. Cardoza-Avendaño, H. Cervantes-de Ávila, J. A. Michel-Macarty, C. Cruz-Hernández, A. Arellano-Delgado, R. Carmona-Rodríguez

Abstract:

In this paper, synchronization of multiple chaotic semiconductor lasers is achieved by appealing to complex system theory. In particular, we consider dynamical networks composed by semiconductor laser, as interconnected nodes, where the interaction in the networks are defined by coupling the first state of each node. An interesting case is synchronized with master-slave configuration in star topology. Nodes of these networks are modeled for the laser and simulated by Matlab. These results are applicable to private communication.

Keywords: chaotic laser, network, star topology, synchronization

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806 Impulsive Synchronization of Periodically Forced Complex Duffing's Oscillators

Authors: Shaban Aly, Ali Al-Qahtani, Houari B. Khenous

Abstract:

Synchronization is an important phenomenon commonly observed in nature. A system of periodically forced complex Duffings oscillators was introduced and shown to display chaotic behavior and possess strange attractors. Such complex oscillators appear in many problems of physics and engineering, as, for example, nonlinear optics, deep-water wave theory, plasma physics and bimolecular dynamics. In this paper, we study the remarkable phenomenon of chaotic synchronization on these oscillator systems, using impulsive synchronization techniques. We derive analytical expressions for impulsive control functions and show that the dynamics of error evolution is globally stable, by constructing appropriate Lyapunov functions. This means that, for a relatively large set initial conditions, the differences between the drive and response systems vanish exponentially and synchronization is achieved. Numerical results are obtained to test the validity of the analytical expressions and illustrate the efficiency of these techniques for inducing chaos synchronization in our nonlinear oscillators.

Keywords: complex nonlinear oscillators, impulsive synchronization, chaotic systems, global exponential synchronization

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805 Chaos in a Stadium-Shaped 2-D Quantum Dot

Authors: Roger Yu

Abstract:

A numerical scheme has been developed to solve wave equations for chaotic systems such as stadium-shaped cavity. The same numerical method can also be used for finding wave properties of rectangle cavities with randomly placed obstacles. About 30k eigenvalues have been obtained accurately on a normal circumstance. For comparison, we also initiated an experimental study which determines both eigenfrequencies and eigenfunctions of a stadium-shaped cavity using pulse and normal mode analyzing techniques. The acoustic cavity was made adjustable so that the transition from nonchaotic (circle) to chaotic (stadium) waves can be investigated.

Keywords: quantum dot, chaos, numerical method, eigenvalues

Procedia PDF Downloads 85
804 Dynamics of Mach Zehnder Modulator in Open and Closed Loop Bias Condition

Authors: Ramonika Sengupta, Stuti Kachhwaha, Asha Adhiya, K. Satya Raja Sekhar, Rajwinder Kaur

Abstract:

Numerous efforts have been done in the past decade to develop the methods of secure communication that are free from interception and eavesdropping. In fiber optic communication, chaotic optical carrier signals are used for data encryption in secure data transmission. Mach-Zehnder Modulators (MZM) are the key components for generating the chaotic signals to be used as optical carriers. This paper presents the dynamics of a lithium niobate MZM modulator under various biasing conditions. The chaotic fluctuations of the intensity of a laser diode have been generated using the electro-optic MZM modulator operating in a highly nonlinear regime. The modulator is driven in closed loop by its own output at an earlier time. When used as an electro-optic oscillator employing delayed feedback, the MZM displays a wide range of output waveforms of varying complexity. The dynamical behavior of the system ranges from periodic to nonlinear oscillations. The nonlinearity displayed by the system is reproducible and is easily controllable. In this paper, we demonstrate a wide variety of optical signals generated by MZM using easily controllable device parameters in both open and close loop bias conditions.

Keywords: chaotic carrier, fiber optic communication, Mach-Zehnder modulator, secure data transmission

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803 Synchronization of Chaotic T-System via Optimal Control as an Adaptive Controller

Authors: Hossein Kheiri, Bashir Naderi, Mohamad Reza Niknam

Abstract:

In this paper we study the optimal synchronization of chaotic T-system with complete uncertain parameter. Optimal control laws and parameter estimation rules are obtained by using Hamilton-Jacobi-Bellman (HJB) technique and Lyapunov stability theorem. The derived control laws are optimal adaptive control and make the states of drive and response systems asymptotically synchronized. Numerical simulation shows the effectiveness and feasibility of the proposed method.

Keywords: Lyapunov stability, synchronization, chaos, optimal control, adaptive control

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802 A Study on ESD Protection Circuit Applying Silicon Controlled Rectifier-Based Stack Technology with High Holding Voltage

Authors: Hee-Guk Chae, Bo-Bae Song, Kyoung-Il Do, Jeong-Yun Seo, Yong-Seo Koo

Abstract:

In this study, an improved Electrostatic Discharge (ESD) protection circuit with low trigger voltage and high holding voltage is proposed. ESD has become a serious problem in the semiconductor process because the semiconductor density has become very high these days. Therefore, much research has been done to prevent ESD. The proposed circuit is a stacked structure of the new unit structure combined by the Zener Triggering (SCR ZTSCR) and the High Holding Voltage SCR (HHVSCR). The simulation results show that the proposed circuit has low trigger voltage and high holding voltage. And the stack technology is applied to adjust the various operating voltage. As the results, the holding voltage is 7.7 V for 2-stack and 10.7 V for 3-stack.

Keywords: ESD, SCR, latch-up, power clamp, holding voltage

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801 An Optimization Tool-Based Design Strategy Applied to Divide-by-2 Circuits with Unbalanced Loads

Authors: Agord M. Pinto Jr., Yuzo Iano, Leandro T. Manera, Raphael R. N. Souza

Abstract:

This paper describes an optimization tool-based design strategy for a Current Mode Logic CML divide-by-2 circuit. Representing a building block for output frequency generation in a RFID protocol based-frequency synthesizer, the circuit was designed to minimize the power consumption for driving of multiple loads with unbalancing (at transceiver level). Implemented with XFAB XC08 180 nm technology, the circuit was optimized through MunEDA WiCkeD tool at Cadence Virtuoso Analog Design Environment ADE.

Keywords: divide-by-2 circuit, CMOS technology, PLL phase locked-loop, optimization tool, CML current mode logic, RF transceiver

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800 A User Interface for Easiest Way Image Encryption with Chaos

Authors: D. López-Mancilla, J. M. Roblero-Villa

Abstract:

Since 1990, the research on chaotic dynamics has received considerable attention, particularly in light of potential applications of this phenomenon in secure communications. Data encryption using chaotic systems was reported in the 90's as a new approach for signal encoding that differs from the conventional methods that use numerical algorithms as the encryption key. The algorithms for image encryption have received a lot of attention because of the need to find security on image transmission in real time over the internet and wireless networks. Known algorithms for image encryption, like the standard of data encryption (DES), have the drawback of low level of efficiency when the image is large. The encrypting based on chaos proposes a new and efficient way to get a fast and highly secure image encryption. In this work, a user interface for image encryption and a novel and easiest way to encrypt images using chaos are presented. The main idea is to reshape any image into a n-dimensional vector and combine it with vector extracted from a chaotic system, in such a way that the vector image can be hidden within the chaotic vector. Once this is done, an array is formed with the original dimensions of the image and turns again. An analysis of the security of encryption from the images using statistical analysis is made and is used a stage of optimization for image encryption security and, at the same time, the image can be accurately recovered. The user interface uses the algorithms designed for the encryption of images, allowing you to read an image from the hard drive or another external device. The user interface, encrypt the image allowing three modes of encryption. These modes are given by three different chaotic systems that the user can choose. Once encrypted image, is possible to observe the safety analysis and save it on the hard disk. The main results of this study show that this simple method of encryption, using the optimization stage, allows an encryption security, competitive with complicated encryption methods used in other works. In addition, the user interface allows encrypting image with chaos, and to submit it through any public communication channel, including internet.

Keywords: image encryption, chaos, secure communications, user interface

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799 Equivalent Circuit Model for the Eddy Current Damping with Frequency-Dependence

Authors: Zhiguo Shi, Cheng Ning Loong, Jiazeng Shan, Weichao Wu

Abstract:

This study proposes an equivalent circuit model to simulate the eddy current damping force with shaking table tests and finite element modeling. The model is firstly proposed and applied to a simple eddy current damper, which is modelled in ANSYS, indicating that the proposed model can simulate the eddy current damping force under different types of excitations. Then, a non-contact and friction-free eddy current damper is designed and tested, and the proposed model can reproduce the experimental observations. The excellent agreement between the simulated results and the experimental data validates the accuracy and reliability of the equivalent circuit model. Furthermore, a more complicated model is performed in ANSYS to verify the feasibility of the equivalent circuit model in complex eddy current damper, and the higher-order fractional model and viscous model are adopted for comparison.

Keywords: equivalent circuit model, eddy current damping, finite element model, shake table test

Procedia PDF Downloads 153
798 Reconsidering Taylor’s Law with Chaotic Population Dynamical Systems

Authors: Yuzuru Mitsui, Takashi Ikegami

Abstract:

The exponents of Taylor’s law in deterministic chaotic systems are computed, and their meanings are intensively discussed. Taylor’s law is the scaling relationship between the mean and variance (in both space and time) of population abundance, and this law is known to hold in a variety of ecological time series. The exponents found in the temporal Taylor’s law are different from those of the spatial Taylor’s law. The temporal Taylor’s law is calculated on the time series from the same locations (or the same initial states) of different temporal phases. However, with the spatial Taylor’s law, the mean and variance are calculated from the same temporal phase sampled from different places. Most previous studies were done with stochastic models, but we computed the temporal and spatial Taylor’s law in deterministic systems. The temporal Taylor’s law evaluated using the same initial state, and the spatial Taylor’s law was evaluated using the ensemble average and variance. There were two main discoveries from this work. First, it is often stated that deterministic systems tend to have the value two for Taylor’s exponent. However, most of the calculated exponents here were not two. Second, we investigated the relationships between chaotic features measured by the Lyapunov exponent, the correlation dimension, and other indexes with Taylor’s exponents. No strong correlations were found; however, there is some relationship in the same model, but with different parameter values, and we will discuss the meaning of those results at the end of this paper.

Keywords: chaos, density effect, population dynamics, Taylor’s law

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797 Analysis of Stacked SCR-Based ESD Protection Circuit with Low Trigger Voltage and Latch-Up Immunity

Authors: Jun-Geol Park, Kyoung-Il Do, Min-Ju Kwon, Kyung-Hyun Park, Yong-Seo Koo

Abstract:

In this paper, we proposed the SCR (Silicon Controlled Rectifier)-based ESD (Electrostatic Discharge) protection circuit for latch-up immunity. The proposed circuit has a lower trigger voltage and a higher holding voltage characteristic by using the zener diode structure. These characteristics prevent latch-up problem in normal operating conditions. The proposed circuit was analyzed to figure out the electrical characteristics by the variations of design parameters D1, D2 and stack technology to obtain the n-fold electrical characteristics. The simulations are accomplished by using the Synopsys TCAD simulator. When using the stack technology, 2-stack has the holding voltage of 6.9V and 3-stack has the holding voltage of 10.9V.

Keywords: ESD, SCR, trigger voltage, holding voltage

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796 Coal Preparation Plant:Technology Overview and New Adaptations

Authors: Amit Kumar Sinha

Abstract:

A coal preparation plant typically operates with multiple beneficiation circuits to process individual size fractions of coal obtained from mine so that the targeted overall plant efficiency in terms of yield and ash is achieved. Conventional coal beneficiation plant in India or overseas operates generally in two methods of processing; coarse beneficiation with treatment in dense medium cyclones or in baths and fines beneficiation with treatment in flotation cell. This paper seeks to address the proven application of intermediate circuit along with coarse and fines circuit in Jamadoba New Coal Preparation Plant of capacity 2 Mt/y to treat -0.5 mm+0.25 mm size particles in reflux classifier. Previously this size of particles was treated directly in Flotation cell which had operational and metallurgical limitations which will be discussed in brief in this paper. The paper also details test work results performed on the representative samples of TSL coal washeries to determine the top size of intermediate and fines circuit and discusses about the overlapping process of intermediate circuit and how it is process wise suitable to beneficiate misplaced particles from coarse circuit and fines circuit. This paper also compares the separation efficiency (Ep) of various intermediate circuit process equipment and tries to validate the use of reflux classifier over fine coal DMC or spirals. An overview of Modern coal preparation plant treating Indian coal especially Washery Grade IV coal with reference to Jamadoba New Coal Preparation Plant which was commissioned in 2018 with basis of selection of equipment and plant profile, application of reflux classifier in intermediate circuit and process design criteria is also outlined in this paper.

Keywords: intermediate circuit, overlapping process, reflux classifier

Procedia PDF Downloads 103
795 Dimensioning of Circuit Switched Networks by Using Simulation Code Based On Erlang (B) Formula

Authors: Ali Mustafa Elshawesh, Mohamed Abdulali

Abstract:

The paper presents an approach to dimension circuit switched networks and find the relationship between the parameters of the circuit switched networks on the condition of specific probability of call blocking. Our work is creating a Simulation code based on Erlang (B) formula to draw graphs which show two curves for each graph; one of simulation and the other of calculated. These curves represent the relationships between average number of calls and average call duration with the probability of call blocking. This simulation code facilitates to select the appropriate parameters for circuit switched networks.

Keywords: Erlang B formula, call blocking, telephone system dimension, Markov model, link capacity

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794 Design of 900 MHz High Gain SiGe Power Amplifier with Linearity Improved Bias Circuit

Authors: Guiheng Zhang, Wei Zhang, Jun Fu, Yudong Wang

Abstract:

A 900 MHz three-stage SiGe power amplifier (PA) with high power gain is presented in this paper. Volterra Series is applied to analyze nonlinearity sources of SiGe HBT device model clearly. Meanwhile, the influence of operating current to IMD3 is discussed. Then a β-helper current mirror bias circuit is applied to improve linearity, since the β-helper current mirror bias circuit can offer stable base biasing voltage. Meanwhile, it can also work as predistortion circuit when biasing voltages of three bias circuits are fine-tuned, by this way, the power gain and operating current of PA are optimized for best linearity. The three power stages which fabricated by 0.18 μm SiGe technology are bonded to the printed circuit board (PCB) to obtain impedances by Load-Pull system, then matching networks are done for best linearity with discrete passive components on PCB. The final measured three-stage PA exhibits 21.1 dBm of output power at 1 dB compression point (OP1dB) with power added efficiency (PAE) of 20.6% and 33 dB power gain under 3.3 V power supply voltage.

Keywords: high gain power amplifier, linearization bias circuit, SiGe HBT model, Volterra series

Procedia PDF Downloads 300
793 Transient Voltage Distribution on the Single Phase Transmission Line under Short Circuit Fault Effect

Authors: A. Kojah, A. Nacaroğlu

Abstract:

Single phase transmission lines are used to transfer data or energy between two users. Transient conditions such as switching operations and short circuit faults cause the generation of the fluctuation on the waveform to be transmitted. Spatial voltage distribution on the single phase transmission line may change owing to the position and duration of the short circuit fault in the system. In this paper, the state space representation of the single phase transmission line for short circuit fault and for various types of terminations is given. Since the transmission line is modeled in time domain using distributed parametric elements, the mathematical representation of the event is given in state space (time domain) differential equation form. It also makes easy to solve the problem because of the time and space dependent characteristics of the voltage variations on the distributed parametrically modeled transmission line.

Keywords: energy transmission, transient effects, transmission line, transient voltage, RLC short circuit, single phase

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792 Protection of the Valves against AC Faults Using the Fast-Acting HVDC Controls

Authors: Mesbah Tarek, Kelaiaia Samia, Chiheb Sofien, Kelaiaia Mounia Samira, Labar Hocine

Abstract:

Short circuit causes important damage in power systems. The aim of this paper is the investigation of the effect of short circuit at the AC side inverter in HVDC transmission line. The cutoff of HVDC transmission line implies important economic losses. In this paper it is proposed an efficient procedure which can protect and eliminate the fault quickly. The theoretical development and simulation are well detailed and illustrated.

Keywords: AC inverter, HVDC, short circuit, switcher gate, power system

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791 Power Supply Feedback Regulation Loop Design Using Cadence PSpice Tool: Determining Converter Stability by Simulation

Authors: Debabrata Das

Abstract:

This paper explains how to design a regulation loop for a power supply circuit. It also discusses the need of a regulation loop and the improvement of a circuit with regulation loop. A sample design is used to demonstrate how to use PSpice to design feedback loop to control output voltage of a power supply and how to check if the power supply is stable or oscillatory. A sample design is made using a specific Integrated Circuit (IC) available in the PSpice library. A designer can experiment feedback loop design using Cadence Pspice tool. PSpice is easy to use, reliable, and convenient. To test a feedback loop, generally, engineers use trial and error method with the hardware which takes a lot of time and manpower. Moreover, it is expensive because component and Printed Circuit Board (PCB) may go bad. PSpice can be used by designers to test their loop designs without using hardware circuits. A designer can save time, cost, manpower and simulate his/her power supply circuit accurately before making a real hardware using this software package.

Keywords: power electronics, feedback loop, regulation, stability, pole, zero, oscillation

Procedia PDF Downloads 318
790 Bridgeless Boost Power Factor Correction Rectifier with Hold-Up Time Extension Circuit

Authors: Chih-Chiang Hua, Yi-Hsiung Fang, Yuan-Jhen Siao

Abstract:

A bridgeless boost (BLB) power factor correction (PFC) rectifier with hold-up time extension circuit is proposed in this paper. A full bridge rectifier is widely used in the front end of the ac/dc converter. Since the shortcomings of the full bridge rectifier, the bridgeless rectifier is developed. A BLB rectifier topology is utilized with the hold-up time extension circuit. Unlike the traditional hold-up time extension circuit, the proposed extension scheme uses fewer active switches to achieve a longer hold-up time. Simulation results are presented to verify the converter performance.

Keywords: bridgeless boost (BLB), boost converter, power factor correction (PFC), hold-up time

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789 The Response of LCC to DC System Faults and HVDC Re-Establishment

Authors: Mesbah Tarek, Kelaiaia Samia, Chiheb Sofien, Kelaiaia Mounia Samira, Labar Hocine

Abstract:

As every power systems short circuit failure can occur for HVDC at the DC link. So, the power devices should be protected against over heath produced by this over-current. This can be achieved through the power switchers or fast breaker. After short circuit the system is unable to restart, only after a time delay, because of the potential distribution along the DC link line. An appropriate fast and safety control is proposed and tested successfully. The detailed development and discussion of these faults is presented in this paper.

Keywords: HVDC, DC link, switchers, short circuit, faults

Procedia PDF Downloads 540
788 Detection of Chaos in General Parametric Model of Infectious Disease

Authors: Javad Khaligh, Aghileh Heydari, Ali Akbar Heydari

Abstract:

Mathematical epidemiological models for the spread of disease through a population are used to predict the prevalence of a disease or to study the impacts of treatment or prevention measures. Initial conditions for these models are measured from statistical data collected from a population since these initial conditions can never be exact, the presence of chaos in mathematical models has serious implications for the accuracy of the models as well as how epidemiologists interpret their findings. This paper confirms the chaotic behavior of a model for dengue fever and SI by investigating sensitive dependence, bifurcation, and 0-1 test under a variety of initial conditions.

Keywords: epidemiological models, SEIR disease model, bifurcation, chaotic behavior, 0-1 test

Procedia PDF Downloads 291
787 Transforming Butterworth Low Pass Filter into Microstrip Line Form at LC-Band Applications

Authors: Liew Hui Fang, Syed Idris Syed Hassan, Mohd Fareq Abd. Malek, Yufridin Wahab, Norshafinash Saudin

Abstract:

The paper implementation new approach method applied into transforming lumped element circuit into microstrip line form for Butterworth low pass filter which is operating at LC band. The filter’s lumped element circuits and microstrip line form were first designed and simulated using Advanced Design Software (ADS) to obtain the best filter characteristic based on S-parameter and implemented on FR4 substrate for order N=3,4,5,6,7,8 and 9. The importance of a new approach of transforming method as a correction factor has been considered into designed microstrip line. From ADS simulation results proved that the response of microstrip line circuit of Butterworth low pass filter with fringing correction factor has an excellent agreement with its lumped circuit. This shows that the new approach of transforming lumped element circuit into microstrip line is able to solve the conventional design of complexity size of circuit of Butterworth low pass filter (LPF) into microstrip line.

Keywords: Butterworth low pass filter, number of order, microstrip line, microwave filter, maximally flat

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786 Control of Chaotic Behaviour in Parallel-Connected DC-DC Buck-Boost Converters

Authors: Ammar Nimer Natsheh

Abstract:

Chaos control is used to design a controller that is able to eliminate the chaotic behaviour of nonlinear dynamic systems that experience such phenomena. The paper describes the control of the bifurcation behaviour of a parallel-connected DC-DC buck-boost converter used to provide an interface between energy storage batteries and photovoltaic (PV) arrays as renewable energy sources. The paper presents a delayed feedback control scheme in a module converter comprises two identical buck-boost circuits and operates in the continuous-current conduction mode (CCM). MATLAB/SIMULINK simulation results show the effectiveness and robustness of the scheme.

Keywords: chaos, bifurcation, DC-DC Buck-Boost Converter, Delayed Feedback Control

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785 The Effects of a Circuit Training Program on Muscle Strength, Agility, Anaerobic Performance and Cardiovascular Endurance

Authors: Wirat Sonchan, Pratoom Moungmee, Anek Sootmongkol

Abstract:

This study aimed to examine the effects of a circuit training program on muscle strength, agility, anaerobic performance and cardiovascular endurance. The study involved 24 freshmen (age 18.87+0.68 yr.) male students of the Faculty of Sport Science, Burapha University. They sample study were randomly divided into two groups: Circuit Training group (CT; n=12) and a Control group (C; n=12). Baseline data on height, weight, muscle strength (hand grip dynamometer and leg strength dynamometer), agility (agility T-Test), and anaerobic performance (Running-based Anaerobic Sprint Test) and cardiovascular endurance (20 m Endurance Shuttle Run Test) were collected. The circuit training program included one circuit of eight stations of 30/60 seconds of work/rest interval with two cycles in Week 1-4, and 60/90 seconds of work/rest interval with three cycles in Week 5-8, performed three times per week. Data were analyzed using paired t-tests and independent sample t-test. Statistically significance level was set at 0.05. The results show that after 8 weeks of a training program, muscle strength, agility, anaerobic capacity and cardiovascular endurance increased significantly in the CT Group (p < 0.05), while significant increase was not observed in the C Group (p < 0.05). The results of this study suggest that the circuit training program improved muscle strength, agility, anaerobic capacity and cardiovascular endurance of the study subjects. This program may be used as a guideline for selecting a set of exercise to improve physical fitness.

Keywords: circuit training, physical fitness, cardiovascular endurance, anaerobic performance

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784 Application on Metastable Measurement with Wide Range High Resolution VDL Circuit

Authors: Po-Hui Yang, Jing-Min Chen, Po-Yu Kuo, Chia-Chun Wu

Abstract:

This paper proposed a high resolution Vernier Delay Line (VDL) measurement circuit with coarse and fine detection mechanism, which improved the trade-off problem between high resolution and less delay cells in traditional VDL circuits. And the measuring time of proposed measurement circuit is also under the high resolution requests. At first, the testing range of input signal which proposed high resolution delay line is detected by coarse detection VDL. Moreover, the delayed input signal is transmitted to fine detection VDL for measuring value with better accuracy. This paper is implemented at 0.18μm process, operating frequency is 100 MHz, and the resolution achieved 2.0 ps with only 16-stage delay cells. The test range is 170ps wide, and 17% stages saved compare with traditional single delay line circuit.

Keywords: vernier delay line, D-type flip-flop, DFF, metastable phenomenon

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783 Self-Organizing Control Systems for Unstable and Deterministic Chaotic Processes

Authors: Mamyrbek A. Beisenbi, Nurgul M. Kissikova, Saltanat E. Beisembina, Salamat T. Suleimenova, Samal A. Kaliyeva

Abstract:

The paper proposes a method for constructing a self-organizing control system for unstable and deterministic chaotic processes in the class of catastrophe “hyperbolic umbilic” for objects with m-inputs and n-outputs. The self-organizing control system is investigated by the universal gradient-velocity method of Lyapunov vector functions. The conditions for self-organization of the control system in the class of catastrophes “hyperbolic umbilic” are shown in the form of a system of algebraic inequalities that characterize the aperiodic robust stability in the stationary states of the system.

Keywords: gradient-velocity method of Lyapunov vector-functions, hyperbolic umbilic, self-organizing control system, stability

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782 Modelisation of a Full-Scale Closed Cement Grinding

Authors: D. Touil, L. Ouadah

Abstract:

An industrial model of cement grinding circuit is proposed on the basis of sampling surveys undertaken in the Meftah cement plant in Algiers, Algeria. The ball mill is described by a series of equal fully mixed stages that incorporates the effect of air sweeping. The kinetic parameters of this material in the energy normalized form obtained using the data of batch dry ball milling are taken into account in developing the present scale-up procedure. The dynamic separator is represented by the air classifier selectivity equation corrected by empirical factors. The model is incorporated in computer program that predict full size distributions and mass flow rates for all streams in a circuit under a particular set of operating conditions.

Keywords: grinding circuit, clinker, cement, modeling, population balance, energy

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781 Modeling and Simulation of a CMOS-Based Analog Function Generator

Authors: Madina Hamiane

Abstract:

Modelling and simulation of an analogy function generator is presented based on a polynomial expansion model. The proposed function generator model is based on a 10th order polynomial approximation of any of the required functions. The polynomial approximations of these functions can then be implemented using basic CMOS circuit blocks. In this paper, a circuit model is proposed that can simultaneously generate many different mathematical functions. The circuit model is designed and simulated with HSPICE and its performance is demonstrated through the simulation of a number of non-linear functions.

Keywords: modelling and simulation, analog function generator, polynomial approximation, CMOS transistors

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780 The Uniting Control Lyapunov Functions in Permanent Magnet Synchronous Linear Motor

Authors: Yi-Fei Yang, Nai-Bao He, Shao-Bang Xing

Abstract:

This study investigates the permanent magnet synchronous linear motor (PMSLM) chaotic motion under the specific physical parameters, the stability and the security of motor-driven system will be unavoidably influenced. Therefore, it is really necessary to investigate the methods of controlling or suppressing chaos in PMSLM. Firstly, we derive a chaotic model of PMSLM in the closed-loop system. Secondly, in order to realize the local asymptotic stabilization of the mechanical subsystem and the global stabilization of the motor-driven system including electrical subsystem, we propose an improved uniting control lyapunov functions by introducing backstepping approach. Finally, an illustrated example is also given to show the electiveness of the obtained results.

Keywords: linear motor, lyapunov functions, chao control, hybrid controller

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779 Identifying Chaotic Architecture: Origins of Nonlinear Design Theory

Authors: Mohammadsadegh Zanganehfar

Abstract:

Since the modernism, movement, and appearance of modern architecture, an aggressive desire for a general design theory in the theoretical works of architects in the form of books and essays emerges. Since Robert Venturi and Denise Scott Brown’s published complexity and contradiction in architecture in 1966, the discourse of complexity and volumetric composition has been an important and controversial issue in the discipline. Ever since various theories and essays were involved in this discourse, this paper attempt to identify chaos theory as a scientific model of complexity and its relation to architecture design theory by conducting a qualitative analysis and multidisciplinary critical approach through architecture and basic sciences resources. As a result, we identify chaotic architecture as the correlation of chaos theory and architecture as an independent nonlinear design theory with specific characteristics and properties.

Keywords: architecture complexity, chaos theory, fractals, nonlinear dynamic systems, nonlinear ontology

Procedia PDF Downloads 337