Search results for: MOSFET

Authors: Zina Saheb, Ezz El-Masry, Jean-François Bousquet

Abstract:

This paper presents an enhanced efficiency simultaneous dual band energy harvesting system for wireless body area network. A bulk biasing is used to enhance the efficiency of the adapted rectifier design to reduce V_th of MOSFET. The presented circuit harvests the radio frequency (RF) energy from two frequency bands: 1 GHz and 2.4 GHz. It is designed with TSMC 65-nm CMOS technology and high quality factor dual matching network to boost the input voltage. Full circuit analysis and modeling is demonstrated. The simulation results demonstrate a harvester with an efficiency of 23% at 1 GHz and 46% at 2.4 GHz at an input power as low as -30 dBm.

Keywords: energy harvester, simultaneous, dual band, CMOS, differential rectifier, voltage boosting, TSMC 65nm

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Authors: Vincent King Soon Wong, Hong Seng Ng, Florinna Sim

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Negative Bias Temperature Instability (NBTI) is one of the critical degradation mechanisms in semiconductor device reliability that causes shift in the threshold voltage (Vth). However, thorough understanding of this reliability failure mechanism is still unachievable due to a recovery characteristic known as NBTI recovery. This paper will demonstrate the severity of NBTI recovery as well as one of the effective methods used to mitigate, which is the minimization of measurement system delays. Comparison was done in between two measurement systems that have significant differences in measurement delays to show how NBTI recovery causes result deviations and how fast measurement systems can mitigate NBTI recovery. Another method to minimize NBTI recovery without the influence of measurement system known as Fast Wafer Level Reliability (FWLR) NBTI was also done to be used as reference.

Keywords: fast vs slow BTI, fast wafer level reliability (FWLR), negative bias temperature instability (NBTI), NBTI measurement system, metal-oxide-semiconductor field-effect transistor (MOSFET), NBTI recovery, reliability

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Authors: L. Ashok Kumar, N. Sujith Kumar

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Most of the PV systems are designed with transformer for safety purpose with galvanic isolation. However, the transformer is big, heavy and expensive. Also, it reduces the overall frequency of the conversion stage. Generally PV inverter with transformer is having efficiency around 92%–94% only. To overcome these problems, transformerless PV system is introduced. It is smaller, lighter, cheaper and higher in efficiency. However, dangerous leakage current will flow between PV array and the grid due to the stray capacitance. There are different types of configurations available for transformerless inverters like H5, H6, HERIC, oH5, and Dual paralleled buck inverter. But each configuration is suffering from its own disadvantages like high conduction losses, shoot-through issues of switches, dead-time requirements at zero crossing instants of grid voltage to avoid grid shoot-through faults and MOSFET reverse recovery issues. The main objective of the proposed transformerless inverter is to address two key issues: One key issue for a transformerless inverter is that it is necessary to achieve high efficiency compared to other existing inverter topologies. Another key issue is that the inverter configuration should not have any shoot-through issues for higher reliability.

Keywords: grid-connected, photovoltaic (PV) systems, transformerless inverter, stray capacitance, common-mode, leakage current, pulse width modulation (PWM)

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Authors: Jun Wang, Tingcun Wei

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The digital pulse width modulator (DPWM) is the crucial building block for digitally-controlled DC-DC switching converter, which converts the digital duty ratio signal into its analog counterpart to control the power MOSFET transistors on or off. With the increase of switching frequency of digitally-controlled DC-DC converter, the DPWM with higher time resolution is required. In this paper, a 15-bits DPWM with three-level hybrid structure is presented; the first level is composed of a7-bits counter and a comparator, the second one is a 5-bits delay line, and the third one is a 3-bits digital dither. The presented DPWM is designed and implemented using the PLL megafunction of FPGA (Field Programmable Gate Arrays), and the required frequency of clock signal is 128 times of switching frequency. The simulation results show that, for the switching frequency of 2 MHz, a DPWM which has the time resolution of 15 ps is achieved using a maximum clock frequency of 256MHz. The designed DPWM in this paper is especially useful for high-frequency digitally-controlled DC-DC switching converters.

Keywords: DPWM, digitally-controlled DC-DC switching converter, FPGA, PLL megafunction, time resolution

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Authors: Fatima Zohra Rahou, A.Guen Bouazza, B. Bouazza

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SOI TRI GATE FinFET transistors have emerged as novel devices due to its simple architecture and better performance: better control over short channel effects (SCEs) and reduced power dissipation due to reduced gate leakage currents. As the oxide thickness scales below 2 nm, leakage currents due to tunneling increase drastically, leading to high power consumption and reduced device reliability. Replacing the SiO2 gate oxide with a high-κ material allows increased gate capacitance without the associated leakage effects. In this paper, SOI TRI-GATE FinFET structure with use of high K dielectric materials (HfO2) and SiO2 dielectric are simulated using the 3-D device simulator Devedit and Atlas of TCAD Silvaco. The simulated results exhibits significant improvements in the performances of SOI TRI GATE FinFET with gate oxide HfO2 compared with conventional gate oxide SiO2 for the same structure. SOI TRI-GATE FinFET structure with the use of high K materials (HfO2) in gate oxide results into the increase in saturation current, threshold voltage, on-state current and Ion/Ioff ratio while off-state current, subthreshold slope and DIBL effect are decreased.

Keywords: technology SOI, short-channel effects (SCEs), multi-gate SOI MOSFET, SOI-TRI Gate FinFET, high-K dielectric, Silvaco software

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Authors: Ravi Kiran Jaladi, Ezz I. El-Masry

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Emerging technologies such as ultra-wide band wireless access technology that operate at ultra-low power present several challenges due to their inherent design that limits the use of voltage-mode filters. Therefore, Continuous-time current-mode (CTCM) filters have become very popular in recent times due to the fact they have a wider dynamic range, improved linearity, and extended bandwidth compared to their voltage-mode counterparts. The goal of this research is to develop analog filters which are suitable for the current scaling CMOS technologies. Bulk-driven MOSFET is one of the most popular low power design technique for the existing challenges, while other techniques have obvious shortcomings. In this work, a CTCM Gate-driven (GD) differentiator has been presented with a frequency range from dc to 100MHz which operates at very low supply voltage of 0.7 volts. A novel CTCM Bulk-driven (BD) differentiator has been designed for the first time which reduces the power consumption multiple times that of GD differentiator. These GD and BD differentiator has been simulated using CADENCE TSMC 65nm technology for all the bilinear and biquadratic band-pass frequency responses. These basic building blocks can be used to implement the higher order filters. A 6th order cascade CTCM Chebyshev band-pass filter has been designed using the GD and BD techniques. As a conclusion, a low power GD and BD 6th order chebyshev stagger-tuned band-pass filter was simulated and all the parameters obtained from all the resulting realizations are analyzed and compared. Monte Carlo analysis is performed for both the 6th order filters and the results of sensitivity analysis are presented.

Keywords: bulk-driven (BD), continuous-time current-mode filters (CTCM), gate-driven (GD)

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Authors: Naima Guenifi, Shiromani Balmukund Rahi, Amina Bechka

Abstract:

Tunnel FET is one of the most suitable alternatives FET devices for conventional CMOS technology for low-power electronics and applications. Due to its lower subthreshold swing (SS) value, it is a strong follower of low power applications. It is a quantum FET device that follows the band to band (B2B) tunneling transport phenomena of charge carriers. Due to band to band tunneling, tunnel FET is suffering from a lower switching current than conventional metal-oxide-semiconductor field-effect transistor (MOSFET). For improvement of device features and limitations, the newly invented negative capacitance concept of ferroelectric material is implemented in conventional Tunnel FET structure popularly known as NC TFET. The present research work has implemented the idea of high-k gate dielectric added with ferroelectric material on double gate Tunnel FET for implementation of negative capacitance. It has been observed that the idea of negative capacitance further improves device features like SS value. It helps to reduce power dissipation and switching energy. An extensive investigation for circularity uses for digital, analog/RF and linearity features of double gate NCTFET have been adopted here for research work. Several essential designs paraments for analog/RF and linearity parameters like transconductance(gm), transconductance generation factor (gm/IDS), its high-order derivatives (gm2, gm3), cut-off frequency (fT), gain-bandwidth product (GBW), transconductance generation factor (gm/IDS) has been investigated for low power RF applications. The VIP₂, VIP₃, IMD₃, IIP₃, distortion characteristics (HD2, HD3), 1-dB, the compression point, delay and power delay product performance have also been thoroughly studied.

Keywords: analog/digital, ferroelectric, linearity, negative capacitance, Tunnel FET, transconductance

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Authors: Udayan Patankar, Shashwati Bhagat, Vilas Nitneware, Ants Koel

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An ISM band power amplifier is a type of electronic amplifier used to convert a low-power radio-frequency signal into a larger signal of significant power, typically used for driving the antenna of a transmitter. Due to drastic changes in telecommunication generations may lead to the requirements of improvements. Rapid changes in communication lead to the wide implementation of WLAN technology for its excellent characteristics, such as high transmission speed, long communication distance, and high reliability. Many applications such as WLAN, Bluetooth, and ZigBee, etc. were evolved with 2.4GHz to 5 GHz ISM Band, in which the power amplifier (PA) is a key building block of RF transmitters. There are many manufacturing processes available to manufacture a power amplifier for desired power output, but the major problem they have faced is about the power it consumed for its proper working, as many of them are fabricated on the GaN HEMT, Bi COMS process. In this paper we present a CMOS Base two stage cascode design of power amplifier working on 2.4GHz ISM frequency band. To lower the costs and allow full integration of a complete System-on-Chip (SoC) we have chosen 0.13µm low power CMOS technology for design. While designing a power amplifier, it is a real task to achieve higher power efficiency with minimum resources. This design showcase the Multi biased Cascode methodology to implement a two-stage CMOS power amplifier using ADS and LTSpice simulating tool. Main source is maximum of 2.4V which is internally distributed into different biasing point VB driving and VB driven as required for distinct stages of two stage RF power amplifier. It shows maximum power added efficiency near about 70.195% whereas its Power added efficiency calculated at 1 dB compression point is 44.669 %. Biased MOSFET is used to reduce total dc current as this circuit is designed for different wireless applications comes under 2.4GHz ISM Band.

Keywords: RFIC, PAE, RF CMOS, impedance matching

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Authors: Osamede Asowata, Christo Pienaar, Johan Bekker

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Photovoltaic (PV) modules may become a trend for future PV systems because of their greater flexibility in distributed system expansion, easier installation due to their nature, and higher system-level energy harnessing capabilities under shaded or PV manufacturing mismatch conditions. This is as compared to the single or multi-string inverters. Novel residential scale PV arrays are commonly connected to the grid by a single DC–AC inverter connected to a series, parallel or series-parallel string of PV panels, or many small DC–AC inverters which connect one or two panels directly to the AC grid. With an increasing worldwide interest in sustainable energy production and use, there is renewed focus on the power electronic converter interface for DC energy sources. Three specific examples of such DC energy sources that will have a role in distributed generation and sustainable energy systems are the photovoltaic (PV) panel, the fuel cell stack, and batteries of various chemistries. A high-efficiency inverter using Metal Oxide Semiconductor Field-Effect Transistors (MOSFETs) for all active switches is presented for a non-isolated photovoltaic and AC-module applications. The proposed configuration features a high efficiency over a wide load range, low ground leakage current and low-output AC-current distortion with no need for split capacitors. The detailed power stage operating principles, pulse width modulation scheme, multilevel bootstrap power supply, and integrated gate drivers for the proposed inverter is described. Experimental results of a hardware prototype, show that not only are MOSFET efficient in the system, it also shows that the ground leakage current issues are alleviated in the proposed inverter and also a 98 % maximum associated driver circuit is achieved. This, in turn, provides the need for a possible photovoltaic panel switching technique. This will help to reduce the effect of cloud movements as well as improve the overall efficiency of the system.

Keywords: grid connected photovoltaic (PV), Matlab efficiency simulation, maximum power point tracking (MPPT), module integrated converters (MICs), multilevel converter, series connected converter

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Authors: Chyuan Haur Kao, Hsiang Chen, Yu Sheng Tsai, Chen Hao Hung, Yu Shan Lee

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Dielectric electrolyte-insulator-semiconductor sensing membranes-based biosensors have been intensively investigated because of their simple fabrication, low cost, and fast response. However, to enhance their sensing performance, it is worthwhile to explore alternative materials, distinct processes, and novel treatments. An ISFET can be viewed as a variation of MOSFET with the dielectric oxide layer as the sensing membrane. Then, modulation on the work function of the gate caused by electrolytes in various ion concentrations could be used to calculate the ion concentrations. Recently, owing to the advancement of CMOS technology, some high dielectric materials substrates as the sensing membranes of electrolyte-insulator-semiconductor (EIS) structures. The EIS with a stacked-layer of SiO₂ layer between the sensing membrane and the silicon substrate exhibited a high pH sensitivity and good long-term stability. IGZO is a wide-bandgap (~3.15eV) semiconductor of the III-VI semiconductor group with several preferable properties, including good transparency, high electron mobility, wide band gap, and comparable with CMOS technology. IGZO was sputtered by reactive radio frequency (RF) on a p-type silicon wafer with various gas ratios of Ar:O₂ and was treated with rapid thermal annealing in O₂ ambient. The sensing performance, including sensitivity, hysteresis, and drift rate was measured and XRD, XPS, and AFM analyses were also used to study the material properties of the IGZO membrane. Moreover, IGZO was used as a sensing membrane in dielectric EIS bio-sensor structures. In addition to traditional pH sensing capability, detection for concentrations of Na+, K+, urea, glucose, and creatinine was performed. Moreover, post rapid thermal annealing (RTA) treatment was confirmed to improve the material properties and enhance the multi-analyte sensing capability for various ions or chemicals in solutions. In this study, the IGZO sensing membrane with annealing in O₂ ambient exhibited a higher sensitivity, higher linearity, higher H+ selectivity, lower hysteresis voltage and lower drift rate. Results indicate that the IGZO dielectric sensing membrane on the EIS structure is promising for future bio-medical device applications.

Keywords: dielectric sensing membrane, IGZO, hydrogen ion, plasma, rapid thermal annealing

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Authors: T. Weber, D. MacKenzie

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The script in this paper describes the use of advanced simulation environment using electronic systems (microcontroller, operational amplifiers, and FPGA). The simulation was used for non-linear dynamic systems behaviour with required observer structure working with parallel real-time simulation based on state-space representation. The proposed deposited model was used for electrodynamic effects including ionising effects and eddy current distribution also. With the script and proposed method, it is possible to calculate the spatial distribution of the electromagnetic fields in real-time and such systems. For further purpose, the spatial temperature distribution may also be used. With upon system, the uncertainties and disturbances may be determined. This provides the estimation of the more precise system states for the required system and additionally the estimation of the ionising disturbances that arise due to radiation effects in space systems. The results have also shown that a system can be developed specifically with the real-time calculation (estimation) of the radiation effects only. Electronic systems can take damage caused by impacts with charged particle flux in space or radiation environment. TID (Total Ionising Dose) of 1 Gy and Single Effect Transient (SET) free operation up to 50 MeVcm²/mg may assure certain functions. Single-Event Latch-up (SEL) results on the placement of several transistors in the shared substrate of an integrated circuit; ionising radiation can activate an additional parasitic thyristor. This short circuit between semiconductor-elements can destroy the device without protection and measurements. Single-Event Burnout (SEB) on the other hand, increases current between drain and source of a MOSFET and destroys the component in a short time. A Single-Event Gate Rupture (SEGR) can destroy a dielectric of semiconductor also. In order to be able to react to these processes, it must be calculated within a shorter time that ionizing radiation and dose is present. For this purpose, sensors may be used for the realistic evaluation of the diffusion and ionizing effects of the test system. For this purpose, the Peltier element is used for the evaluation of the dynamic temperature increases (dT/dt), from which a measure of the ionization processes and thus radiation will be detected. In addition, the piezo element may be used to record highly dynamic vibrations and oscillations to absorb impacts of charged particle flux. All available sensors shall be used to calibrate the spatial distributions also. By measured value of size and known location of the sensors, the entire distribution in space can be calculated retroactively or more accurately. With the formation, the type of ionisation and the direct effect to the systems and thus possible prevent processes can be activated up to the shutdown. The results show possibilities to perform more qualitative and faster simulations independent of space-systems and radiation environment also. The paper gives additionally an overview of the diffusion effects and their mechanisms.

Keywords: cattle, biochar, manure, microbial activity

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Authors: Ramesh P., Aby Joseph

Abstract:

Micro Inverters provide Module Embedded Solution for harvesting energy from small-scale solar photovoltaic (PV) panels. In addition to higher modularity & reliability (25 years of life), the MicroInverter has inherent advantages such as avoidance of long DC cables, eliminates module mismatch losses, minimizes partial shading effect, improves safety and flexibility in installations etc. Due to the above-stated benefits, the renewable energy technology with Solar Photovoltaic (PV) Micro Inverter becomes more widespread in Village Nano Grid application ensuring grid independence for rural communities and areas without access to electricity. While the primary objective of this paper is to discuss the problems related to rural electrification, this concept can also be extended to urban installation with grid connectivity. This work presents a comprehensive analysis of the power circuit design, control methodologies and prototyping of 300Wₚ Single Phase PV Micro Inverter. This paper investigates two different topologies for PV Micro Inverters, based on the first hand on Single Stage Flyback/ Forward PV Micro-Inverter configuration and the other hand on the Double stage configuration including DC-DC converter, H bridge DC-AC Inverter. This work covers Power Decoupling techniques to reduce the input filter capacitor size to buffer double line (100 Hz) ripple energy and eliminates the use of electrolytic capacitors. The propagation of the double line oscillation reflected back to PV module will affect the Maximum Power Point Tracking (MPPT) performance. Also, the grid current will be distorted. To mitigate this issue, an independent MPPT control algorithm is developed in this work to reject the propagation of this double line ripple oscillation to PV side to improve the MPPT performance and grid side to improve current quality. Here, the power hardware topology accepts wide input voltage variation and consists of suitably rated MOSFET switches, Galvanically Isolated gate drivers, high-frequency magnetics and Film capacitors with a long lifespan. The digital controller hardware platform inbuilt with the external peripheral interface is developed using floating point microcontroller TMS320F2806x from Texas Instruments. The firmware governing the operation of the PV Micro Inverter is written in C language and was developed using code composer studio Integrated Development Environment (IDE). In this work, the prototype hardware for the Single Phase Photovoltaic Micro Inverter with Double stage configuration was developed and the comparative analysis between the above mentioned configurations with experimental results will be presented.

Keywords: double line oscillation, micro inverter, MPPT, nano grid, power decoupling

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