Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 6

Search results for: K. Kaouther

6 A Nanoindentation Study of Thin Film Prepared by Physical Vapor Deposition

Authors: Dhiflaoui Hafedh, Ben Cheikh Larbi Ahmed, Khlifi Kaouther


Monolayer and multilayer coatings of CrN and AlCrN deposited on 100Cr6 (AISI 52100) substrate by PVD magnetron sputtering system. The micro structures of the coatings were characterized using atomic force microscopy (AFM). The AFM analysis revealed the presence of domes and craters which are uniformly distributed over all surfaces of the various layers. Nano indentation measurement of CrN coating showed maximum hardness (H) and modulus (E) of 14 GPa and 240 GPa, respectively. The measured H and E values of AlCrN coatings were found to be 30 GPa and 382 GPa, respectively. The improved hardness in both the coatings was attributed mainly to a reduction in crystallite size and decrease in surface roughness. The incorporation of Al into the CrN coatings has improved both hardness and Young’s modulus.

Keywords: Hardness, Nanoindentation, CrN, AlCrN coatings

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5 Use of Hierarchical Temporal Memory Algorithm in Heart Attack Detection

Authors: Tesnim Charrad, Kaouther Nouira, Ahmed Ferchichi


In order to reduce the number of deaths due to heart problems, we propose the use of Hierarchical Temporal Memory Algorithm (HTM) which is a real time anomaly detection algorithm. HTM is a cortical learning algorithm based on neocortex used for anomaly detection. In other words, it is based on a conceptual theory of how the human brain can work. It is powerful in predicting unusual patterns, anomaly detection and classification. In this paper, HTM have been implemented and tested on ECG datasets in order to detect cardiac anomalies. Experiments showed good performance in terms of specificity, sensitivity and execution time.

Keywords: ECG, HTM, cardiac anomalies, real time anomaly detection

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4 Mechanical Behavior of PVD Single Layer and Multilayer under Indentation Tests

Authors: K. Kaouther, D. Hafedh, A. Ben Cheikh Larbi


Various structures and compositions thin films were deposited on 100C6 (AISI 52100) steel substrate by PVD magnetron sputtering system. The morphological proprieties were evaluated using an atomic force microscopy (AFM). Vickers microindentation tests were performed with a Shimadzu HMV-2000 hardness testing machine. Hardness measurement was carried out using Jonsson and Hogmark model. The results show that the coatings topography was dominated by domes and craters. Mechanical behavior and failure modes under microindentation were depending of coatings structure and composition. TiAlN multilayer showed exception in the microindentation resistance compared to TiN single layer and TiAlN/TiAlN nanolayer. Piled structure provides an increase of failure resistance and a decrease in cracks propagation.

Keywords: cracking, Multilayer, Damage Mechanisms, PVD thin films, microindentation

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3 Core Number Optimization Based Scheduler to Order/Mapp Simulink Application

Authors: Asma Rebaya, Kaouther Gasmi, Imen Amari, Salem Hasnaoui


Over these last years, the number of cores witnessed a spectacular increase in digital signal and general use processors. Concurrently, significant researches are done to get benefit from the high degree of parallelism. Indeed, these researches are focused to provide an efficient scheduling from hardware/software systems to multicores architecture. The scheduling process consists on statically choose one core to execute one task and to specify an execution order for the application tasks. In this paper, we describe an efficient scheduler that calculates the optimal number of cores required to schedule an application, gives a heuristic scheduling solution and evaluates its cost. Our proposal results are evaluated and compared with Preesm scheduler results and we prove that ours allows better scheduling in terms of latency, computation time and number of cores.

Keywords: Optimization, Scheduling, latency, hardware/software system, multi-cores platform, computation time

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2 Using the SMT Solver to Minimize the Latency and to Optimize the Number of Cores in an NoC-DSP Architectures

Authors: Asma Rebaya, Imen Amari, Salem Hasnaoui, Kaouther Gasmi


The problem of scheduling and mapping data flow applications on multi-core architectures is notoriously difficult. This difficulty is related to the rapid evaluation of Telecommunication and multimedia systems accompanied by a rapid increase of user requirements in terms of latency, execution time, consumption, energy, etc. Having an optimal scheduling on multi-cores DSP (Digital signal Processors) platforms is a challenging task. In this context, we present a novel technic and algorithm in order to find a valid schedule that optimizes the key performance metrics particularly the Latency. Our contribution is based on Satisfiability Modulo Theories (SMT) solving technologies which is strongly driven by the industrial applications and needs. This paper, describe a scheduling module integrated in our proposed Workflow which is advised to be a successful approach for programming the applications based on NoC-DSP platforms. This workflow transform automatically a Simulink model to a synchronous dataflow (SDF) model. The automatic transformation followed by SMT solver scheduling aim to minimize the final latency and other software/hardware metrics in terms of an optimal schedule. Also, finding the optimal numbers of cores to be used. In fact, our proposed workflow taking as entry point a Simulink file (.mdl or .slx) derived from embedded Matlab functions. We use an approach which is based on the synchronous and hierarchical behavior of both Simulink and SDF. Whence, results of running the scheduler which exist in the Workflow mentioned above using our proposed SMT solver algorithm refinements produce the best possible scheduling in terms of latency and numbers of cores.

Keywords: Scheduling, workflow, multi-cores DSP, SMT solver

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1 An Efficient Hardware/Software Workflow for Multi-Cores Simulink Applications

Authors: Asma Rebaya, Kaouther Gasmi, Imen Amari, Salem Hasnaoui


Over these last years, applications such as telecommunications, signal processing, digital communication with advanced features (Multi-antenna, equalization..) witness a rapid evaluation accompanied with an increase of user exigencies in terms of latency, the power of computation… To satisfy these requirements, the use of hardware/software systems is a common solution; where hardware is composed of multi-cores and software is represented by models of computation, synchronous data flow (SDF) graph for instance. Otherwise, the most of the embedded system designers utilize Simulink for modeling. The issue is how to simplify the c code generation, for a multi-cores platform, of an application modeled by Simulink. To overcome this problem, we propose a workflow allowing an automatic transformation from the Simulink model to the SDF graph and providing an efficient schedule permitting to optimize the number of cores and to minimize latency. This workflow goes from a Simulink application and a hardware architecture described by IP.XACT language. Based on the synchronous and hierarchical behavior of both models, the Simulink block diagram is automatically transformed into an SDF graph. Once this process is successfully achieved, the scheduler calculates the optimal cores’ number needful by minimizing the maximum density of the whole application. Then, a core is chosen to execute a specific graph task in a specific order and, subsequently, a compatible C code is generated. In order to perform this proposal, we extend Preesm, a rapid prototyping tool, to take the Simulink model as entry input and to support the optimal schedule. Afterward, we compared our results to this tool results, using a simple illustrative application. The comparison shows that our results strictly dominate the Preesm results in terms of number of cores and latency. In fact, if Preesm needs m processors and latency L, our workflow need processors and latency L'< L.

Keywords: Modeling, workflow, latency, hardware/software system, multi-cores platform, scheduler, SDF graph, Simulink model

Procedia PDF Downloads 130