Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 2
Search results for: Jaouhar Mouine
2 Implementation of a Baseline RISC for the Realization of a Dynamically Reconfigurable Processor
Authors: Hajer Najjar, Riad Bourguiba, Jaouhar Mouine
Abstract:
Reduced instruction set computer (RISC) processors are widely used because of their multiple advantages. In fact, they are based on a simple instruction set so that they increase the speed of the processor and reduce its energy consumption. In this paper, we will present a basic RISC architecture processor that will be developed later to converge to a new architecture with runtime reconfiguration.Keywords: processor, RISC, DLX, pipeline, runtime reconfiguration
Procedia PDF Downloads 3671 The Design and Implementation of an Enhanced 2D Mesh Switch
Authors: Manel Langar, Riad Bourguiba, Jaouhar Mouine
Abstract:
In this paper, we propose the design and implementation of an enhanced wormhole virtual channel on chip router. It is a heart of a mesh NoC using the XY deterministic routing algorithm. It is characterized by its simple virtual channel allocation strategy which allows reducing area and complexity of connections without affecting the performance. We implemented our router on a Tezzaron process to validate its performances. This router is a basic element that will be used later to design a 3D mesh NoC.Keywords: NoC, mesh, router, 3D NoC
Procedia PDF Downloads 523