Search results for: GATE Developer

Authors: Zina Saheb, Ezz El-Masry

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As CMOS technology scaling down, Silicon oxide thickness (SiO2) become very thin (few Nano meters). When SiO2 is less than 3nm, gate direct tunneling (DT) leakage current becomes a dormant problem that impacts the transistor performance. Floating gate MOSFET (FGMOSFET) has been used in many low-voltage and low-power applications. Most of the available simulation models of FGMOSFET for analog circuit design does not account for gate DT current and there is no accurate analysis for the gate DT. It is a crucial to use an accurate mode in order to get a realistic simulation result that account for that DT impact on FGMOSFET performance effectively.

Keywords: CMOS transistor, direct-tunneling current, floating-gate, gate-leakage current, simulation model

Procedia PDF Downloads 501

Authors: Yun-Hsuan Yu, Chi-Shung Tang, Nzar Rauf Abdullah, Vidar Gudmundsson

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Spin-orbit gap feature in energy dispersion of one-dimensional devices is revealed via strong spin-orbit interaction (SOI) effects under Zeeman field. We describe the utilization of a finger-gate or a top-gate to control the spin-dependent transport characteristics in the SOI-Zeeman influenced split-gate devices by means of a generalized spin-mixed propagation matrix method. For the finger-gate system, we find a bound state in continuum for incident electrons within the ultra-low energy regime. For the top-gate system, we observe more bound-state features in conductance associated with the formation of spin-associated hole-like or electron-like quasi-bound states around band thresholds, as well as hole bound states around the reverse point of the energy dispersion. We demonstrate that the spin-dependent transport behavior of a top-gate system is similar to that of a finger-gate system only if the top-gate length is less than the effective Fermi wavelength.

Keywords: spin-orbit, zeeman, top-gate, finger-gate, bound state

Procedia PDF Downloads 232

Authors: Fatima Zohra Rahou, A.Guen Bouazza, B. Bouazza

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SOI TRI GATE FinFET transistors have emerged as novel devices due to its simple architecture and better performance: better control over short channel effects (SCEs) and reduced power dissipation due to reduced gate leakage currents. As the oxide thickness scales below 2 nm, leakage currents due to tunneling increase drastically, leading to high power consumption and reduced device reliability. Replacing the SiO2 gate oxide with a high-κ material allows increased gate capacitance without the associated leakage effects. In this paper, SOI TRI-GATE FinFET structure with use of high K dielectric materials (HfO2) and SiO2 dielectric are simulated using the 3-D device simulator Devedit and Atlas of TCAD Silvaco. The simulated results exhibits significant improvements in the performances of SOI TRI GATE FinFET with gate oxide HfO2 compared with conventional gate oxide SiO2 for the same structure. SOI TRI-GATE FinFET structure with the use of high K materials (HfO2) in gate oxide results into the increase in saturation current, threshold voltage, on-state current and Ion/Ioff ratio while off-state current, subthreshold slope and DIBL effect are decreased.

Keywords: technology SOI, short-channel effects (SCEs), multi-gate SOI MOSFET, SOI-TRI Gate FinFET, high-K dielectric, Silvaco software

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Authors: A. Douara, N. Kermas, B. Djellouli

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In this study, we report calculations of gate capacitance of AlGaN/GaN HEMTs with nextnano device simulation software. We have used a physical gate capacitance model for III-V FETs that incorporates quantum capacitance and centroid capacitance in the channel. These simulations explore various device structures with different values of barrier thickness and channel thickness. A detailed understanding of the impact of gate capacitance in HEMTs will allow us to determine their role in future 10 nm physical gate length node.

Keywords: gate capacitance, AlGaN/GaN, HEMTs, quantum capacitance, centroid capacitance

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Authors: Mahendrapal Singh Pachlaniya, Laxmi Kumre

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The AOI (AND – OR- INVERTER) based design of XOR gate is proposed in this paper with less number of gates. This new XOR gate required four basic gates and basic gate include only AND, OR, Inverter (AOI). Conventional XOR gate required five basic gates. Ripple Carry Adder (RCA) used in parallel addition but propagation delay time is large. RCA replaced with Carry Select Adder (CSLA) to reduce propagation delay time. CSLA design with dual RCA considering carry = ‘0’ and carry = ‘1’, so it is not an area efficient adder. To make area efficient, modified CSLA is designed with single RCA considering carry = ‘0’ and another RCA considering carry = ‘1’ replaced with Binary to Excess 1 Converter (BEC). Now replacement of conventional XOR gate by new design of XOR gate in modified CSLA reduces much area compared to regular CSLA and modified CSLA.

Keywords: CSLA, BEC, XOR gate, area efficient

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Authors: Sangeeta Singh, Pankaj Kumar, P. N. Kondekar

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In this paper, the transient device performance analysis of n-type Gate Inside Junctionless Transistor (GIJLT)has been evaluated. 3-D Bohm Quantum Potential (BQP)transport device simulation has been used to evaluate the delay and power dissipation performance. GI-JLT has a number of desirable device parameters such as reduced propagation delay, dynamic power dissipation, power and delay product, intrinsic gate delay and energy delay product as compared to Gate-all-around transistors GAA-JLT. In addition to this, various other device performance parameters namely, on/off current ratio, short channel effects (SCE), transconductance Generation Factor(TGF) and unity gain cut-off frequency (fT) and subthreshold slope (SS) of the GI-JLT and Gate-all-around junctionless transistor(GAA-JLT) have been analyzed and compared. GI-JLT shows better device performance characteristics than GAA-JLT for low power and high frequency applications, because of its larger gate electrostatic control on the device operation.

Keywords: gate-inside junctionless transistor GI-JLT, gate-all-around junctionless transistor GAA-JLT, propagation delay, power delay product

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Authors: Porag Jyoti Ligira, Gargi Khanna

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The paper presents a simulation study of the electrical characteristic of Bulk Planar Junctionless Transistor (BPJLT) using spacer. The BPJLT is a transistor without any PN junctions in the vertical direction. It is a gate controlled variable resistor. The characteristics of BPJLT are analyzed by varying the oxide material under the gate. It can be shown from the simulation that an ideal subthreshold slope of ~60 mV/decade can be achieved by using highk dielectric. The effects of variation of spacer length and material on the electrical characteristic of BPJLT are also investigated in the paper. The ION / IOFF ratio improvement is of the order of 107 and the OFF current reduction of 10-4 is obtained by using gate dielectric of HfO2 instead of SiO2.

Keywords: spacer, BPJLT, high-k, double gate

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Authors: Dheeraj Sharma, Santosh Kumar Vishvakarma

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We present a detailed analysis of analog and radiofrequency (RF) performance with different gate lengths for nanowire cylindrical gate (CylG) gate-all-around (GAA) MOSFET. CylG GAA MOSFET not only suppresses the short channel effects (SCEs), it is also a good candidate for analog/RF device due to its high transconductance (gm) and high cutoff frequency (fT ). The presented work would be beneficial for a new generation of RF circuits and systems in a broad range of applications and operating frequency covering the RF spectrum. For this purpose, the analog/RF figures of merit for CylG GAA MOSFET is analyzed in terms of gate to source capacitance (Cgs), gate to drain capacitance (Cgd), transconductance generation factor gm = Id (where Id represents drain current), intrinsic gain, output resistance, fT, maximum frequency of oscillation (fmax) and gain bandwidth (GBW) product.

Keywords: Gate-All-Around MOSFET, GAA, output resistance, transconductance generation factor, intrinsic gain, cutoff frequency, fT

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Authors: Roumaissa Derdour, Lebbal Mohamed Redha

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We present a study of the transmission of the all-optical logic gate using a structure connected with a triangular photonic crystal lattice that is improved. The proposed logic gate consists of a photonic crystal nano-resonator formed by changing the size of the air holes. In addition to the simplicity, the response time is very short, and the designed nano-resonator increases the bit rate of the logic gate. The two-dimensional finite difference time domain (2DFDTD) method is used to simulate the structure; the transmission obtained is about 98% with very negligible losses. The proposed photonic crystal AND logic gate is widely used in future integrated optical microelectronics.

Keywords: logic gates, photonic crystals, optical integrated circuits, resonant cavities

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Authors: Michael K. Adu, Boniface K. Alese, Olumide S. Ogunnusi

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This paper brings to fore the inherent advantages in application of mobile agents to procure software products rather than downloading software content on the Internet. It proposes a system whereby the products come on compact disk with mobile agent as deliverable. The client/user purchases a software product, but must connect to the remote server of the software developer before installation. The user provides an activation code that activates mobile agent which is part of the software product on compact disk. The validity of the activation code is checked on connection at the developer’s end to ascertain authenticity and prevent piracy. The system is implemented by downloading two different software products as compare with installing same products on compact disk with mobile agent’s application. Downloading software contents from developer’s database as in the traditional method requires a continuously open connection between the client and the developer’s end, a fixed network is not economically or technically feasible. Mobile agent after being dispatched into the network becomes independent of the creating process and can operate asynchronously and autonomously. It can reconnect later after completing its task and return for result delivery. Response Time and Network Load are very minimal with application of Mobile agent.

Keywords: software products, software developer, internet, activation code, mobile agent

Procedia PDF Downloads 263

Authors: A. A. Akande, B. P. Dhonge, B. W. Mwakikunga, A. G. J. Machatine

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This article presents gate-voltage controlled humidity sensing performance of vanadium dioxide nanoparticles prepared from NH₄VO₃ precursor using microwave irradiation technique. The X-ray diffraction, transmission electron diffraction, and Raman analyses reveal the formation of VO₂ (B) with V₂O₅ and an amorphous phase. The BET surface area is found to be 67.67 m²/g. The humidity sensing measurements using the patented lateral-gate MOSFET configuration was carried out. The results show the optimum response at 5 V up to 8 V of gate voltages for 10 to 80% of relative humidity. The dose-response equation reveals the enhanced resilience of the gated VO₂ sensor which may saturate above 272% humidity. The response and recovery times are remarkably much faster (about 60 s) than in non-gated VO₂ sensors which normally show response and recovery times of the order of 5 minutes (300 s).

Keywords: VO2, VO2(B), MOSFET, gate voltage, humidity sensor

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Authors: Svetlana Strinyuk, Viacheslav Lanin

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Academic English has become lingua franca for international scientific community which stimulates universities to introduce English for Specific Purposes (EAP) courses into curriculum. Teaching L2 EAP students might be fulfilled with corpus technologies and digital stylistics. A special software developed to reach the manifold task of teaching, assessing and researching academic writing of L2 students on basis of digital stylistics and multidimensional analysis was created. A set of annotations (style markers) – grammar, lexical and syntactic features most significant of academic writing was built. Contrastive comparison of two corpora “model corpus”, subject domain limited papers published by competent writers in leading academic journals, and “students’ corpus”, subject domain limited papers written by last year students allows to receive data about the features of academic writing underused or overused by L2 EAP student. Both corpora are tagged with a special software created in GATE Developer. Style markers within the framework of research might be replaced depending on the relevance and validity of the result which is achieved from research corpora. Thus, selecting relevant (high frequency) style markers and excluding less relevant, i.e. less frequent annotations, high validity of the model is achieved. Software allows to compare the data received from processing model corpus to students’ corpus and get reports which can be used in teaching and assessment. The less deviation from the model corpus students demonstrates in their writing the higher is academic writing skill acquisition. The research showed that several style markers (hedging devices) were underused by L2 EAP students whereas lexical linking devices were used excessively. A special software implemented into teaching of EAP courses serves as a successful visual aid, makes assessment more valid; it is indicative of the degree of writing skill acquisition, and provides data for further research.

Keywords: corpus technologies in EAP teaching, multidimensional analysis, GATE Developer, corpus stylistics

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Authors: Asma Ashoul

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Nowadays, smartphones are playing a major role in our lives, by communicating with family, friends or using them to learn different things in life. Using smartphones to learn and teach today is something common to see in places like schools or colleges. Therefore, thinking about developing an app that teaches Arabic language may help some categories in society to learn a second language. For example, kids under the age of five or older would learn fast by using smartphones. The problem is based on the Arabic language, which is most like to be not used anymore. The developer assumed to develop an app that would help the younger generation on their learning the Arabic language. A research was completed about user interface design to help the developer choose appropriate layouts and designs. Developing the artefact contained different stages. First, analyzing the requirements with the client, which is needed to be developed. Secondly, designing the user interface design based on the literature review. Thirdly, developing and testing the application after it is completed contacting all the tools that have been used. Lastly, evaluation and future recommendation, which contained the overall view about the application followed by the client’s feedback. Gathering the requirements after having client meetings based on the interface design. The project was done following an agile development methodology. Therefore, this methodology helped the developer to manage to finish the work on time.

Keywords: developer, application, interface design, layout, Agile, client

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Authors: Fatima Zohra Rahou, A. Guen Bouazza, B. Bouazza

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Multi-gate SOI MOSFETs has shown better results in subthreshold performances. The replacement of SiO2 by high-k dielectric can fulfill the requirements of Multi-gate MOSFETS with a scaling trend in device dimensions. The advancement in fabrication technology has also boosted the use of different high -k dielectric materials as oxide layer at different places in MOSFET structures. One of the most important multi-gate structures is square GAA SOI MOSFET that is a strong candidate for the next generation nanoscale devices; show an even stronger control of short channel effects. In this paper, GAA SOI MOSFET structure with using high -k dielectrics materials Al2O3 (k~9), HfO2 (k~20), La2O3 (k~30) and metal gate TiN are simulated by using 3-D device simulator DevEdit and Atlas of SILVACO TCAD tools. Square GAA SOI MOSFET transistor with High-k HfO2 gate dielectrics and TiN metal gate exhibits significant improvements performances compared to Al2O3 and La2O3 dielectrics for the same structure. Simulation results of GAA SOI MOSFET transistor with HfO2 dielectric show the increase in saturation current and Ion/Ioff ratio while leakage current, subthreshold slope and DIBL effect are decreased.

Keywords: technology SOI, short-channel effects (SCEs), multi-gate SOI MOSFET, square GAA SOI MOSFET, high-k dielectric, Silvaco software

Procedia PDF Downloads 219

Authors: Kiurski S. Jelena, Ranogajec G. Jonjaua, Oros B. Ivana, Kecić S. Vesna

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The adsorption efficiency of fired clayey pellets of 5 and 8 mm diameter size for Cu(II) and Zn(II) ions removal from a waste printing developer was studied. In order to investigate the influence of contact time, adsorbent mass and pellet size on the adsorption efficiency the batch mode was carried out. Faster uptake of copper ions was obtained with the fired clay pellets of 5 mm diameter size within 30 minutes. The pellets of 8 mm diameter size showed the higher equilibrium time (60 to 75 minutes) for copper and zinc ions. The results pointed out that adsorption efficiency increases with the increase of adsorbent mass. The maximal efficiency is different for Cu(II) and Zn(II) ions due to the pellet size. Therefore, the fired clay pellets of 5 mm diameter size present an effective adsorbent for Cu(II) ions removal (adsorption efficiency is 63.6%), whereas the fired clay pellets of 8 mm diameter size are the best alternative for Zn(II) ions removal (adsorption efficiency is 92.8%) from a waste printing developer.

Keywords: adsorption efficiency, clayey pellet, metal ions, waste printing developer

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Authors: Birinderjit Singh Kalyan, Inderpreet Kaur, Balwinder Singh Sohi

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In this paper, an equivalent model for floating gate transistor has been proposed. Using the floating gate voltage value, capacitive coupling coefficients has been found at different bias conditions. The amount of charge present on the gate has been then calculated using the transient models of hot electron programming and Fowler-Nordheim Tunnelling. The proposed model can be extended to the transient conditions as well. The SPICE equivalent model is designed and current-voltage characteristics and Transfer characteristics are comparatively analysed. The dc current-voltage characteristics, as well as dc transfer characteristics, have been plotted for an FGMOS with W/L=0.25μm/0.375μm, the inter-poly capacitance of 0.8fF for both programmed and erased states. The Comparative analysis has been made between the present model and capacitive coefficient coupling methods which were already available.

Keywords: FGMOS, floating gate transistor, capacitive coupling coefficient, SPICE model

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Authors: Carla Pérez-Chirinos Buxadé, Bruno Fernández-Valdés, Mónica Morral-Yepes, Sílvia Tuyà Viñas, Josep Maria Padullés Riu, Gerard Moras Feliu

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There is a long way to explore all the possible applications inertial measurement units (IMUs) have in the sports field. The aim of this study was to evaluate the validity of a new application on the use of these wearable sensors, specifically it was to evaluate a magnet-based timing system (M-BTS) for timing gate-to-gate in an alpine ski slalom using the magnetometer embedded in an IMU. This was a validation study. The criterion validity of time measured by the M-BTS was assessed using the 95% error range against actual time obtained from photocells. The experiment was carried out with first-and second-year junior skiers performing a ski slalom on a ski training slope. Eight alpine skiers (17.4 ± 0.8 years, 176.4 ± 4.9 cm, 67.7 ± 2.0 kg, 128.8 ± 26.6 slalom FIS-Points) participated in the study. An IMU device was attached to the skier’s lower back. Skiers performed a 40-gate slalom from which four gates were assessed. The M-BTS consisted of placing four bar magnets buried into the snow surface on the inner side of each gate’s turning pole; the magnetometer built into the IMU detected the peak-shaped magnetic field when passing near the magnets at a certain speed. Four magnetic peaks were detected. The time compressed between peaks was calculated. Three inter-gate times were obtained for each system: photocells and M-BTS. The total time was defined as the time sum of the inter-gate times. The 95% error interval for the total time was 0.050 s for the ski slalom. The M-BTS is valid for timing gate-to-gate in an alpine ski slalom. Inter-gate times can provide additional data for analyzing a skier’s performance, such as asymmetries between left and right foot.

Keywords: gate crossing time, inertial measurement unit, timing system, wearable sensor

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Authors: Nikhil Jain, Bin Yu

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We explore the potential of using ultra-thin hexagonal boron nitride (h-BN) as both supporting substrate and gate dielectric for graphene-channel field effect transistors (GFETs). Different from commonly used oxide-based dielectric materials which are typically amorphous, very rough in surface, and rich with surface traps, h-BN is layered insulator free of dangling bonds and surface states, featuring atomically smooth surface. In a graphene-channel-last device structure with local buried metal gate electrode (TiN), thin h-BN multilayer is employed as both supporting “substrate” and gate dielectric for graphene active channel. We observed superior carrier mobility and electrical conduction, significantly improved from that in GFETs with SiO2 as substrate/gate insulator. In addition, we report excellent dielectric behavior of layered h-BN, including ultra-low leakage current and high critical electric field for breakdown.

Keywords: graphene, field-effect transistors, hexagonal boron nitride, dielectric strength, tunneling

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Authors: Dawit Burusie Abdi, Mamidala Jagadesh Kumar

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In this paper, using 2D TCAD simulations, the application of a dual material gate (DMG) for suppressing ambipolar conduction in a tunnel field effect transistor (TFET) is demonstrated. Using the proposed DMG concept, the ambipolar conduction can be effectively suppressed even if the drain doping is as high as that of the source doping. Achieving this symmetrical doping, without the ambipolar conduction in TFETs, gives the advantage of realizing both n-type and p-type devices with the same doping sequences. Furthermore, the output characteristics of the DMG TFET exhibit a good saturation when compared to that of the gate-drain underlap approach. This improved behavior of the DMG TFET makes it a good candidate for inverter based logic circuits.

Keywords: dual material gate, suppressing ambipolar current, symmetrically doped TFET, tunnel FETs, PNPN TFET

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Authors: Junhong Feng, Wenyu Lu, Xinhong Cheng, Li Zheng, Yuehui Yu

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The effects of proton irradiation on the properties of gate oxide were evaluated by monitoring the static parameters (such as threshold voltage and on-resistance) and dynamic parameters (Miller plateau time) of 1700V SiC VDMOS before and after proton irradiation. The incident proton energy was 3MeV, and the doses were 5 × 10¹² P / cm², 1 × 10¹³ P / cm², respectively. The results show that the threshold voltage of MOS exhibits negative drift under proton irradiation, and the near-interface traps in the gate oxide layer are occupied by holes generated by the ionization effect of irradiation, thus forming more positive charges. The basis for selecting TMiller is that the change time of Vgs is the time when Vds just shows an upward trend until it rises to a stable value. The degradation of the turn-off time of the Miller platform verifies that the capacitance Cgd becomes larger, reflecting that the gate oxide layer is introduced into the trap by the displacement effect caused by proton irradiation, and the interface state deteriorates. As a more sensitive area in the irradiation process, the gate oxide layer will be optimized for its parameters (such as thickness, type, etc.) in subsequent studies.

Keywords: SiC VDMOS, proton radiation, Miller time, gate oxide

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Authors: Magdalena Wilk-Kozubek, Magdalena Rowińska, Krzysztof Rola, Joanna Cybińska

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Leuco dye-based thermochromic systems are classified as intelligent materials because they exhibit thermally induced color changes. Thanks to this feature, they are mainly used as temperature sensors in many industrial sectors. For example, placing a thermochromic material on a chemical reactor may warn about exceeding the maximum permitted temperature for a chemical process. Usually two components, a color former and a developer are needed to produce a system with irreversible color change. The color former is an electron donating (proton accepting) compound such as fluoran leuco dye. The developer is an electron accepting (proton donating) compound such as organic carboxylic acid. When the developer melts, the color former - developer complex is created and the termochromic system becomes colored. Typically, the melting point of the applied developer determines the temperature at which the color change occurs. When the lactone ring of the color former is closed, then the dye is in its colorless state. The ring opening, induced by the addition of a proton, causes the dye to turn into its colored state. Since the color former and the developer are often solid, they can be incorporated into polymer films to facilitate their practical use in industry. The objective of this research was to fabricate a leuco dye-based termochromic system that will irreversibly change color after reaching the temperature of 100°C. For this purpose, benzofluoran leuco dye (as color former) and phenoxyacetic acid (as developer with a melting point of 100°C) were introduced into the polymer films during the drop casting process. The film preparation process was optimized in order to obtain thin films with appropriate properties such as transparency, flexibility and homogeneity. Among the optimized factors were the concentration of benzofluoran leuco dye and phenoxyacetic acid, the type, average molecular weight and concentration of the polymer, and the type and concentration of the surfactant. The selected films, containing benzofluoran leuco dye and phenoxyacetic acid, were combined by mild heat treatment. Structural characterization of single and combined films was carried out by FTIR spectroscopy, morphological analysis was performed by optical microscopy and SEM, phase transitions were examined by DSC, color changes were investigated by digital photography and UV-Vis spectroscopy, while emission changes were studied by photoluminescence spectroscopy. The resulting thermochromic system is colorless at room temperature, but after reaching 100°C the developer melts and it turns irreversibly pink. Therefore, it could be used as an additional sensor to warn against boiling of water in power plants using water cooling. Currently used electronic temperature indicators are prone to faults and unwanted third-party actions. The sensor constructed in this work is transparent, thanks to which it can be unnoticed by an outsider and constitute a reliable reference for the person responsible for the apparatus.

Keywords: color developer, leuco dye, thin film, thermochromism

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Authors: Kiurski S. Jelena, Ranogajec G. Jonjaua, Kecić S. Vesna, Oros B. Ivana

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The present study investigates the effectiveness of newly designed clayey pellets (fired clay pellets diameter sizes of 5 and 8 mm, and unfired clay pellets with the diameter size of 15 mm) as the beds in the column adsorption process. The adsorption experiments in the batch mode were performed before the column experiment with the purpose to determine the order of adsorbent package in the column which was to be designed in the investigation. The column experiment was performed by using a known mass of the clayey beds and the volume of the waste printing developer, which was purified. The column was filled in the following order: fired clay pellets of the diameter size of 5 mm, fired clay pellets of the diameter size of 8 mm, and unfired clay pellets of the diameter size of 15 mm. The selected order of the adsorbents showed a high removal efficiency for zinc (97.8%) and copper (81.5%) ions. These efficiencies were better than those in the case of the already existing mode adsorption. The obtained experimental data present a good basis for the selection of an appropriate column fill, but further testing is necessary in order to obtain more accurate results.

Keywords: clay materials, fix bed adsorption column, metal ions, printing developer

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Authors: Kaivan Karami, Sahalu Hassan, Sanna Taking, Afesome Ofiare, Aniket Dhongde, Abdullah Al-Khalidi, Edward Wasige

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We have made a comparative study on the influence of Al₂O₃ and HfO₂ grown using atomic layer deposition (ALD) technique as dielectric in the AlGaN/GaN metal oxide semiconductor high electron mobility transistor (MOS-HEMT) structure. Five samples consisting of 20 nm and 10 nm each of Al₂O₃ and HfO₂ respectively and a Schottky gate HEMT, were fabricated and measured. The threshold voltage shifts towards negative by 0.1 V and 1.8 V for 10 nm thick HfO2 and 10 nm thick Al₂O₃ gate dielectric layers respectively. The negative shift for the 20 nm HfO2 and 20 nm Al₂O₃ were 1.2 V and 4.9 V respectively. Higher gm/IDS (transconductance to drain current) ratio was also obtained in HfO₂ than Al₂O₃. With both materials as dielectric, a significant reduction in the gate leakage current in the order of 10^4 was obtained compared to the sample without the dielectric material.

Keywords: AlGaN/GaN HEMTs, Al2O3, HfO2, MOSHEMTs.

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Authors: Omyma Alosaimi, Asma Alsumait

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The website developer and designer should follow usability guidelines to provide a user-friendly interface. Many guidelines and heuristics have been developed by previous studies to help both the developer and designer in this task, but E-government websites are special cases that require specialized guidelines. This paper introduces a set of eighteen guidelines for evaluating the usability of e-government websites in general and Arabic e-government websites specifically, along with a check list of how to apply them. The validity and effectiveness of these guidelines were evaluated against a variety of user characteristics. The results indicated that the proposed set of guidelines can be used to identify qualitative similarities and differences with user testing and that the new set is best suited for evaluating general and e-governmental usability.

Keywords: e-government, human computer interaction, usability evaluation, usability guidelines

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Authors: N. Massoum, B. Bouazza

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In this paper, we have developed a numerical simulation model to describe the electrical properties of GaInP MESFET with submicron gate (Lg = 0.5 µm). This model takes into account the three-dimensional (3D) distribution of the load in the short channel and the law effect of mobility as a function of electric field. Simulation software based on a stochastic method such as Monte Carlo has been established. The results are discussed and compared with those of the experiment. The result suggests experimentally that, in a very small gate length in our devices (smaller than 40 nm), short-channel tunneling explains the degradation of transistor performance, which was previously enhanced by velocity overshoot.

Keywords: Monte Carlo simulation, transient electron transport, MESFET device, simulation software

Procedia PDF Downloads 478

Authors: Le Chen

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This paper presents an efficient tool platform scheme to ensure quality protection throughout the software development process. The main principle is to manage the information of requirements, design, development, testing, operation and maintenance process with proper tools, and to set up the quality standards of each process. Through the tools’ display and summary of quality standards, the quality standards can be visualizad and ready for policy decision, which is called Quality Gate in this paper. In addition, the tools are also integrated to achieve the exchange and relation of information which highly improving operational efficiency. In this paper, the feasibility of the scheme is verified by practical application of development projects, and the overall information display and data mining are proposed to be further improved.

Keywords: efficiency, quality gate, software process, tools

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Authors: Kunal Das, Priya Sengupta, Abhishek K. Singh

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Pin assignment, scheduling, routing and error detection for arbitrary biochemical protocols in Digital Microfluidic Biochip have been reported in this paper. The research work is concentrating on pin assignment for 2 or 3 droplets routing in the arbitrary biochemical protocol, scheduling and routing in m × n biochip. The volumetric error arises due to droplet split in the biochip. The volumetric error detection is also addressed using biochip AND logic gate which is known as microfluidic AND or mAND gate. The algorithm for pin assignment for m × n biochip required m+n-1 numbers of pins. The basic principle of this algorithm is that no same pin will be allowed to be placed in the same column, same row and diagonal and adjacent cells. The same pin should be placed a distance apart such that interference becomes less. A case study also reported in this paper.

Keywords: digital microfludic biochip, cross-contamination, pin assignment, microfluidic AND gate

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Authors: Lincoln Panjaitan, Antonius Sumarlin

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The development of property businesses in the metropolitan area is growing rapidly forcing big real estate developers to come up with various strategies in winning the heart of consumers. This empirical research is focusing on how the two schools of marketing thoughts; namely, Modern and postmodern marketing employed by the preceding developers to retain consumers’ commitment toward their prospective brands. The data was collected from three different properties of PT. Intiland Tbk using accidental sampling technique. The data of 600 respondents was then put into Structural Equation Model (SEM). The result of the study suggests that both schools of thought can equally produce commitment and loyalty of consumers; however, the difference lays where the loyalty belongs to. The first is more toward developer’s brand and the latter is more toward the co-creation value of the housing community.

Keywords: consumer loyalty, consumer commitment, knowledge sharing platform, marketing mix

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Authors: C. S Lee, W. C. Hsu, H. Y. Liu, C. J. Lin, S. C. Yao, Y. T. Shen, Y. C. Lin

Abstract:

In₀.₁₈Al₀.₈₂N/AlN/GaN metal-oxide-semiconductor heterostructure field-effect transistors (MOS-HFETs) having Al₂O₃ gate-dielectric and backside metal-trench structure are investigated. The Al₂O₃ gate oxide was formed by using a cost-effective non-vacuum ultrasonic spray pyrolysis deposition (USPD) method. In order to enhance the heat dissipation efficiency, metal trenches were etched 3-µm deep and evaporated with a 150-nm thick Ni film on the backside of the Si substrate. The present In₀.₁₈Al₀.₈₂N/AlN/GaN MOS-HFET (Schottky-gate HFET) has demonstrated improved maximum drain-source current density (IDS, max) of 1.08 (0.86) A/mm at VDS = 8 V, gate-voltage swing (GVS) of 4 (2) V, on/off-current ratio (Ion/Ioff) of 8.9 × 10⁸ (7.4 × 10⁴), subthreshold swing (SS) of 140 (244) mV/dec, two-terminal off-state gate-drain breakdown voltage (BVGD) of -191.1 (-173.8) V, turn-on voltage (Von) of 4.2 (1.2) V, and three-terminal on-state drain-source breakdown voltage (BVDS) of 155.9 (98.5) V. Enhanced power performances, including saturated output power (Pout) of 27.9 (21.5) dBm, power gain (Gₐ) of 20.3 (15.5) dB, and power-added efficiency (PAE) of 44.3% (34.8%), are obtained. Superior breakdown and RF power performances are achieved. The present In₀.₁₈Al₀.₈₂N/AlN/GaN MOS-HFET design with backside metal-trench is advantageous for high-power circuit applications.

Keywords: backside metal-trench, InAlN/AlN/GaN, MOS-HFET, non-vacuum ultrasonic spray pyrolysis deposition

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Authors: Debabrata Bhadra, B. K. Chaudhuri

Abstract:

The operation of organic thin film transistors (OFETs) with low voltage is currently a prevailing issue. We have fabricated anthracene thin-film transistor (TFT) with an ultrathin layer (~450nm) of Poly-vinylidene fluoride (PVDF)/CuO nanocomposites as a gate insulator. We obtained a device with excellent electrical characteristics at low operating voltages (<1V). Different layers of the film were also prepared to achieve the best optimization of ideal gate insulator with various static dielectric constant (εr ). Capacitance density, leakage current at 1V gate voltage and electrical characteristics of OFETs with a single and multi layer films were investigated. This device was found to have highest field effect mobility of 2.27 cm2/Vs, a threshold voltage of 0.34V, an exceptionally low sub threshold slope of 380 mV/decade and an on/off ratio of 106. Such favorable combination of properties means that these OFETs can be utilized successfully as voltages below 1V. A very simple fabrication process has been used along with step wise poling process for enhancing the pyroelectric effects on the device performance. The output characteristic of OFET after poling were changed and exhibited linear current-voltage relationship showing the evidence of large polarization. The temperature dependent response of the device was also investigated. The stable performance of the OFET after poling operation makes it reliable in temperature sensor applications. Such High-ε CuO/PVDF gate dielectric appears to be highly promising candidates for organic non-volatile memory and sensor field-effect transistors (FETs).

Keywords: organic field effect transistors, thin film transistor, gate dielectric, organic semiconductor

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