Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 2

parity bits Related Abstracts

2 Simulation of Communication and Sensing Device in Automobiles Using VHDL

Authors: Anirudh Bhaikhel

Abstract:

The exclusive objective of this paper is to develop a device which can pass on the interpreted result of the sensed information to the interfaced communicable devices to avoid or minimise accidents. This device may also be used in case of emergencies like kidnapping, robberies, medical emergencies etc. The present era has seen a rapid metamorphosis in the automobile industry with increasing use of technology and speed. The increase in purchasing power of customers and price war of automobile companies has made an easy access to the automobile users. The use of automobiles has increased tremendously in last 4-5 years thus causing traffic congestions and thus making vehicles more prone to accidents. This device can be an effective measure to counteract cases of abduction. Risks of accidents can be decreased tremendously through the notifications received by these alerts. It will help to detect the upcoming emergencies. This paper includes the simulation of the communication and sensing device required in automobiles using VHDL.

Keywords: Communication, Sensors, Component, Automobiles, cyclic redundancy check (CRC), modulo-2 arithmetic, parity bits, receiver, transmitter, turns, VHDL (VHSIC hardware descriptive language)

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1 Error Detection and Correction for Onboard Satellite Computers Using Hamming Code

Authors: Rafsan Al Mamun, Md. Motaharul Islam, Rabana Tajrin, Nabiha Noor, Shafinaz Qader

Abstract:

In an attempt to enrich the lives of billions of people by providing proper information, security and a way of communicating with others, the need for efficient and improved satellites is constantly growing. Thus, there is an increasing demand for better error detection and correction (EDAC) schemes, which are capable of protecting the data onboard the satellites. The paper is aimed towards detecting and correcting such errors using a special algorithm called the Hamming Code, which uses the concept of parity and parity bits to prevent single-bit errors onboard a satellite in Low Earth Orbit. This paper focuses on the study of Low Earth Orbit satellites and the process of generating the Hamming Code matrix to be used for EDAC using computer programs. The most effective version of Hamming Code generated was the Hamming (16, 11, 4) version using MATLAB, and the paper compares this particular scheme with other EDAC mechanisms, including other versions of Hamming Codes and Cyclic Redundancy Check (CRC), and the limitations of this scheme. This particular version of the Hamming Code guarantees single-bit error corrections as well as double-bit error detections. Furthermore, this version of Hamming Code has proved to be fast with a checking time of 5.669 nanoseconds, that has a relatively higher code rate and lower bit overhead compared to the other versions and can detect a greater percentage of errors per length of code than other EDAC schemes with similar capabilities. In conclusion, with the proper implementation of the system, it is quite possible to ensure a relatively uncorrupted satellite storage system.

Keywords: Satellite, Hamming code, parity bits, low earth orbit, bit-flips, single error upset

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