Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 4

interconnects Related Abstracts

4 Graphene/h-BN Heterostructure Interconnects

Authors: Bin Yu, Yang Xu, Nikhil Jain

Abstract:

The material behavior of graphene, a single layer of carbon lattice, is extremely sensitive to its dielectric environment. We demonstrate improvement in electronic performance of graphene nanowire interconnects with full encapsulation by lattice-matching, chemically inert, 2D layered insulator hexagonal boron nitride (h- BN). A novel layer-based transfer technique is developed to construct the h-BN/MLG/h-BN heterostructures. The encapsulated graphene wires are characterized and compared with that on SiO2 or h-BN substrate without passivating h-BN layer. Significant improvements in maximum current-carrying density, breakdown threshold, and power density in encapsulated graphene wires are observed. These critical improvements are achieved without compromising the carrier transport characteristics in graphene. Furthermore, graphene wires exhibit electrical behavior less insensitive to ambient conditions, as compared with the non-passivated ones. Overall, h-BN/graphene/h- BN heterostructure presents a robust material platform towards the implementation of high-speed carbon-based interconnects.

Keywords: Graphene, interconnects, two-dimensional nanosheet, hexagonal boron nitride, heterostructure

Procedia PDF Downloads 187
3 Two-Dimensional Nanostack Based On Chip Wiring

Authors: Bin Yu, Nikhil Jain

Abstract:

The material behavior of graphene, a single layer of carbon lattice, is extremely sensitive to its dielectric environment. We demonstrate improvement in electronic performance of graphene nanowire interconnects with full encapsulation by lattice-matching, chemically inert, 2D layered insulator hexagonal boron nitride (h-BN). A novel layer-based transfer technique is developed to construct the h-BN/MLG/h-BN heterostructures. The encapsulated graphene wires are characterized and compared with that on SiO2 or h-BN substrate without passivating h-BN layer. Significant improvements in maximum current-carrying density, breakdown threshold, and power density in encapsulated graphene wires are observed. These critical improvements are achieved without compromising the carrier transport characteristics in graphene. Furthermore, graphene wires exhibit electrical behavior less insensitive to ambient conditions, as compared with the non-passivated ones. Overall, h-BN/graphene/h-BN heterostructure presents a robust material platform towards the implementation of high-speed carbon-based interconnects.

Keywords: Graphene, interconnects, two-dimensional nanosheet, hexagonal boron nitride, heterostructure

Procedia PDF Downloads 329
2 High Temperature Oxidation of Cr-Steel Interconnects in Solid Oxide Fuel Cells

Authors: Taha Mattar, Azza Ahmed, Saeed Ghali

Abstract:

Solid Oxide Fuel Cell (SOFC) is a promising solution for the energy resources leakage. Ferritic stainless steel becomes a suitable candidate for the SOFCs interconnects due to the recent advancements. Different steel alloys were designed to satisfy the needed characteristics in SOFCs interconnect as conductivity, thermal expansion and corrosion resistance. Refractory elements were used as alloying elements to satisfy the needed properties. The oxidation behaviour of the developed alloys was studied where the samples were heated for long time period at the maximum operating temperature to simulate the real working conditions. The formed scale and oxidized surface were investigated by SEM. Microstructure examination was carried out for some selected steel grades. The effect of alloying elements on the behaviour of the proposed interconnects material and the performance during the working conditions of the cells are explored and discussed. Refractory metals alloying of chromium steel seems to satisfy the needed characteristics in metallic interconnects.

Keywords: interconnects, Oxidation, SOFCs, Cr-steel

Procedia PDF Downloads 184
1 Signal Integrity Performance Analysis in Capacitive and Inductively Coupled Very Large Scale Integration Interconnect Models

Authors: Mudavath Raju, Bhaskar Gugulothu, B. Rajendra Naik

Abstract:

The rapid advances in Very Large Scale Integration (VLSI) technology has resulted in the reduction of minimum feature size to sub-quarter microns and switching time in tens of picoseconds or even less. As a result, the degradation of high-speed digital circuits due to signal integrity issues such as coupling effects, clock feedthrough, crosstalk noise and delay uncertainty noise. Crosstalk noise in VLSI interconnects is a major concern and reduction in VLSI interconnect has become more important for high-speed digital circuits. It is the most effectively considered in Deep Sub Micron (DSM) and Ultra Deep Sub Micron (UDSM) technology. Increasing spacing in-between aggressor and victim line is one of the technique to reduce the crosstalk. Guard trace or shield insertion in-between aggressor and victim is also one of the prominent options for the minimization of crosstalk. In this paper, far end crosstalk noise is estimated with mutual inductance and capacitance RLC interconnect model. Also investigated the extent of crosstalk in capacitive and inductively coupled interconnects to minimizes the same through shield insertion technique.

Keywords: interconnects, VLSI, Signal Integrity, crosstalk, shield insertion, guard trace, deep sub micron

Procedia PDF Downloads 65