%0 Journal Article
	%A Mehdi Hosseinzadeh and  Amir Sabbagh Molahosseini and  Keivan Navi
	%D 2009
	%J International Journal of Computer and Information Engineering
	%B World Academy of Science, Engineering and Technology
	%I Open Science Index 31, 2009
	%T A Parallel Implementation of the Reverse Converter for the Moduli Set {2n, 2n–1, 2n–1–1}
	%U https://publications.waset.org/pdf/4526
	%V 31
	%X In this paper, a new reverse converter for the moduli set {2n, 2n–1, 2n–1–1} is presented. We improved a previously introduced conversion algorithm for deriving an efficient hardware design for reverse converter. Hardware architecture of the proposed converter is based on carry-save adders and regular binary adders, without the requirement for modular adders. The presented design is faster than the latest introduced reverse converter for moduli set {2n, 2n–1, 2n–1–1}. Also, it has better performance than the reverse converters for the recently introduced moduli set {2n+1–1, 2n, 2n–1}

	%P 1790 - 1794