Schmitt Trigger Based SRAM Using Finfet Technology- Shorted Gate Mode
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Schmitt Trigger Based SRAM Using Finfet Technology- Shorted Gate Mode

Authors: Vasundara Patel K. S., Harsha N. Bhushan, Kiran G. Gadag, Nischal Prasad B. N., Mohmmed Haroon

Abstract:

The most widely used semiconductor memory types are the Dynamic Random Access Memory (DRAM) and Static Random Access memory (SRAM). Competition among memory manufacturers drives the need to decrease power consumption and reduce the probability of read failure. A technology that is relatively new and has not been explored is the FinFET technology. In this paper, a single cell Schmitt Trigger Based Static RAM using FinFET technology is proposed and analyzed. The accuracy of the result is validated by means of HSPICE simulations with 32nm FinFET technology and the results are then compared with 6T SRAM using the same technology.

Keywords: Schmitt trigger based SRAM, FinFET, and Static Noise Margin.

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1337287

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References:


[1] UjwalShirode, Ajay Gadhe, "Read stability and read failure analysis of low voltage Schmitt Trigger based SRAM bit cell”, International Journal of Engineering Research and Applications (IJERA) Vol.3, Issue 1, January-February 2013W.-K. Chen, Linear Networks and Systems (Book style). Belmont, CA: Wadsworth, 1993, pp. 123–135.
[2] "International Technology Road map for Semiconductors”, 2006.
[3] K. Bernstein, D. J. Frank, A. E. Gattiker, W. Haensch, B.L. Ji, S. R. Nassif, E. J. Nowak, D. J. Pearson, and N. J.Rohrer, "High-performance CMOS variability in the 65-nm regime and beyond”, IBM J.Res. Dev., vol. 50, no. 4/5, pp. 433–449, Jul./Sep. 2006.
[4] N. Collaert, N. A. De Keersgieter, A. Dixit, I. erain, L.-S. Lai, D. Lenoble, A. Mercha, A. Nackaerts, B.J. Pawlak, R. Rooyackers, T. Schulz, K.T. Sar, N.J. Son, M.J.H. Van Dal, P. Verheyen, K von Arnim, L. Witters, M. De, S.Biesemans, M. Jurczak, "Multi-gate devices for the 32nm technology node and beyond”, Solid State Device Research Conference, 2007. ESSDERC 2007. 37th European,vol.,no., pp.143-146, 11-13 Sept. 2007
[5] K. Noda, T. Uchida, T. Tatsumi, T. Aoyama, K.Nakajima, H. Miyamoto, T. Hashimoto, and I. Sasake, "0.1pm delta-doped MOSFET using post-energy implanting selective epitaxy”, in 1994- VLSI Symp. VLSI Technology Dig. Tech. Papers, pp. 19-20.R. Yan, A. Ourmazd, and K. Lee, "Scaling the Si MOSFET: From bulk to SO1 to bulk”, IEEE Trans. Electron Devices, vol. 39, pp. 1704-1710, July 1992.
[6] F. Assaderaghi, D. Sinitsky, S. A. Parke, J. Bokor, P.KO, and C. Hu, "A dynamic-threshold MOSFET for ultra-low voltage operation”,Znt. Electron Devices Meet. Tech. Dig., 1994, pp. 809-812.
[7] D. Hisamoto, W. C. Lee, J. Kedzierski, H. Takeuchi, K.Asano, C. Kuo, T.-J.King, J. Bokor, and C. Hu, "A folded channel MOSFET for deepsub- tenth micron era”, in IED MTech. Dig., 1998, pp. 1032–1034.
[8] D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K.Asano, C. Kuo, T.-J.King, J. Bokor, and C. Hu, "A folded channel MOSFET for deepsub- tenth micron era,” in IED MTech. Dig., 1998, pp. 1032–1034.
[9] Prateek Mishra, AnishMuttreja, and Niraj K. Jha"FinFET Circuit Design”, Nano Electronics circuit design, 2011, Springer, pp. 23-54
[10] Munish Kumar, ParminderKaur, SheenuThapar, "Design of CMOS Schmitt Trigger”, International Journal of Engineering and Innovative Technology (IJEIT) Volume 2, Issue 1, July 2012.
[11] Jaydeep P. Kulkarn, Keejong Kim, and Kaushik Roy, "A 160 mV Robust Schmitt Trigger Based Sub threshold SRAM” IEEE Journal Of Solid-State Circuits, Vol. 42, No. 10, October 2007.
[12] E. Seevinck, F. List, and J. Lohstroh, "Static noise margin analysis of MOS SRAM cells”, IEEE Solid-State Circuits, vol. SC-22, no. 5, Oct. 1987, 748–754.
[13] BOOK title, "CMOS digital integrated circuits: analysis and design”, Authored Sung-Mo Kang, Yusuf Leblebici.
[14] BOOK title, "CMOS circuit design, layout and simulation”, Volume 1, Authored R. Jacob Baker.
[15] Pilo, H., Barwin, C., Braceras, G., Browning, C., Lamphier, S., Towler, F. "An SRAM Design in 65-nm Technology Node Featuring Read and Write-Assist Circuits to Expand Operating Voltage”, IEEE Journal of Solid-State Circuits. 42. 4. 813 - 819 (Apr. 2007).
[16] F. J. List, "TheStatic Noise Margin of SRAM cells,” in Dig. Tech. Papers, ESSCIRC (Delft, The Netherlands), Sept. 1986, pp. 16–18.