TY - JFULL AU - Ankit Mitra PY - 2014/5/ TI - Design and Analysis of an 8T Read Decoupled Dual Port SRAM Cell for Low Power High Speed Applications T2 - International Journal of Electronics and Communication Engineering SP - 702 EP - 706 VL - 8 SN - 1307-6892 UR - https://publications.waset.org/pdf/9998119 PU - World Academy of Science, Engineering and Technology NX - Open Science Index 88, 2014 N2 - Speed, power consumption and area, are some of the most important factors of concern in modern day memory design. As we move towards Deep Sub-Micron Technologies, the problems of leakage current, noise and cell stability due to physical parameter variation becomes more pronounced. In this paper we have designed an 8T Read Decoupled Dual Port SRAM Cell with Dual Threshold Voltage and characterized it in terms of read and write delay, read and write noise margins, Data Retention Voltage and Leakage Current. Read Decoupling improves the Read Noise Margin and static power dissipation is reduced by using Dual-Vt transistors. The results obtained are compared with existing 6T, 8T, 9T SRAM Cells, which shows the superiority of the proposed design. The Cell is designed and simulated in TSPICE using 90nm CMOS process. ER -