P. Prasad Rao and K. Lal Kishore, Optimizing the Number of Bits/Stage in 10-Bit, 50Ms/Sec Pipelined A/D Converter Considering Area, Speed, Power and Linearity. journal = {International Journal of Electronics and Communication Engineering}, [online]. World Academy of Science, Engineering and Technology. February 2012, vol. 62(2). 211 - 217 [viewed 20 September 2024]. Available from: https://publications.waset.org/pdf/9288.