@article{(Open Science Index):https://publications.waset.org/pdf/9288,
	  title     = {Optimizing the Number of Bits/Stage in 10-Bit, 50Ms/Sec Pipelined A/D Converter Considering Area, Speed, Power and Linearity},
	  author    = {P. Prasad Rao and  K. Lal Kishore},
	  country	= {},
	  institution	= {},
	  abstract     = {Pipeline ADCs are becoming popular at high speeds
and with high resolution. This paper discusses the options of number
of bits/stage conversion techniques in pipelined ADCs and their
effect on Area, Speed, Power Dissipation and Linearity. The basic
building blocks like op-amp, Sample and Hold Circuit, sub converter,
DAC, Residue Amplifier used in every stage is assumed to be
identical. The sub converters use flash architectures. The design is
implemented using 0.18},
	    journal   = {International Journal of Electronics and Communication Engineering},
	  volume    = {6},
	  number    = {2},
	  year      = {2012},
	  pages     = {211 - 217},
	  ee        = {https://publications.waset.org/pdf/9288},
	  url   	= {https://publications.waset.org/vol/62},
	  bibsource = {https://publications.waset.org/},
	  issn  	= {eISSN: 1307-6892},
	  publisher = {World Academy of Science, Engineering and Technology},
	  index 	= {Open Science Index 62, 2012},
	}