Decoder Design for a New Single Error Correcting/Double Error Detecting Code

Authors: M. T. Anwar, P. K. Lala, P. Thenappan

Abstract:

This paper presents the decoder design for the single error correcting and double error detecting code proposed by the authors in an earlier paper. The speed of error detection and correction of a code is largely dependent upon the associated encoder and decoder circuits. The complexity and the speed of such circuits are determined by the number of 1?s in the parity check matrix (PCM). The number of 1?s in the parity check matrix for the code proposed by the authors are fewer than in any currently known single error correcting/double error detecting code. This results in simplified encoding and decoding circuitry for error detection and correction.

Keywords: Decoder, Hsiao code, Parity Check Matrix, Syndrome Pattern.

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1329328

References:

[1] M. Hsiao, "A class of optimal minimum odd-weight-column sec-ded codes," IBM J. Res. Dev., vol. 14, pp. 395-401, July 1970.
[2] D. Pradhan, Fault-Tolerant Computer System Design. Upper Saddle River, NJ: Prentice Hall, 1996.
[3] T. Rao and E. Fujiwara, Error-Control Coding for Computer Systems. Upper Saddle River, NJ: Prentice Hall, 1989.
[4] P.K. Lala, P. Thenappan, and M. Anwar, "Single error correcting and double error detecting coding scheme," IEE Electronics Letters, vol. 41, pp. 758-760, June 2005.