Multi-board Run-time Reconfigurable Implementation of Intrinsic Evolvable Hardware
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Multi-board Run-time Reconfigurable Implementation of Intrinsic Evolvable Hardware

Authors: Cyrille Lambert, Tatiana Kalganova, Emanuele Stomeo, Manissa Wilson

Abstract:

A multi-board run-time reconfigurable (MRTR) system for evolvable hardware (EHW) is introduced with the aim to implement on hardware the bidirectional incremental evolution (BIE) method. The main features of this digital intrinsic EHW solution rely on the multi-board approach, the variable chromosome length management and the partial configuration of the reconfigurable circuit. These three features provide a high scalability to the solution. The design has been written in VHDL with the concern of not being platform dependant in order to keep a flexibility factor as high as possible. This solution helps tackling the problem of evolving complex task on digital configurable support.

Keywords: Evolvable Hardware, Evolutionary Strategy, multiboardFPGA system.

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1329254

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References:


[1] Yao, X., Higuchi, T.: Promises and Challenges of Evolvable Hardware. IEEE Trans. Systems, Man and Cybernetics, Part C, Vol. 29 (1999) 87 - 97
[2] Goldberg, D. E.: Genetic Algorithm in Search, Optimization and Machine Learning. Addison-Wesley Publishing Company, Incorporated, Reading, Massachusetts (1989)
[3] Macias, N. J.: The PIG Paradigm: the Design and Use of a Massively Parallel Fine Grained Self-Reconfigurable Infinitely Scalable Architecture. Proc. of the First NASA/DoD Conf. on Evolvable Hardware, 19-21 (1999) 175 - 180
[4] Ozsvald, I.: Short-Circuiting the Design Process: Evolutionary Algorithms for Circuit Design Using Reconfigurable Analogue Hardware. Masters Thesis (1998)
[5] Stoica, A., Keymeulen, D., Vu, D., Zebulum, R., Ferguson, I., Daud, T., Arsian, T., Xin, G.: Evolutionary Recovery of Electronic Circuits from Radiation Induced Faults. CEC2004 conf. on Evolutionary Computation, Congress on, Vol.: 2, 19-23. Vol.2 (2004) 1786 - 1793
[6] Langeheine, J., Meier, K., Schemmel, J., Trefzer, M.: Intrinsic Evolution of Digital-to-Analog Converters Using a CMOS FPTA Chip. Proc. of the Sixth NASA/DoD Conf. on Evolvable Hardware, 24-26 (2004) 18 - 25
[7] Torresen, J.: Evolving Both Hardware Subsystems and the Selection of Variants of Such Into An Assembled System. In proc. of 16th European Simulation Multiconference. Darmstadt, Germany (2002) 451 - 457
[8] Baumgarte, V., May, F., N├╝ckel, A., Vorbach, M., Weinhardt, M.: PACT XPP - A self-Reconfigurable Data Processing Architecture. Presented at ERSA, Las Vegas, NV, (c) CSREA Press (2001)
[9] Layzell, P.: Reducing Hardware Evolution-s Dependency on FPGAs. In proc. of MicroNeuro-99, 7th International Conference on Microelectronics for Neural, Fuzzy and Bio-inspired Systems, IEEE, Computer Society, CA (1999) 171 - 178
[10] Friedl, S., Sekanina, L.: The First Circuits Evolved in a Physical Virtual Reconfigurable Device. In: Proc. of the 7th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, Bratislava, SK, SAV. ISBN 80-969117-9-(2004) 35 - 42
[11] Glette, K., Torresen, J.: A Flexible On-Chip Evolution System Implemented on a Xilinx Virtex-II Pro Device. ICES (2005) 66 - 75
[12] Sekanina, L.: Towards Evolvable IP Cores for FPGAs. Proc. of the Fifth NASA/DoD Conf. on Evolvable Hardware, Los Alamitos, USA, ICSP, ISBN 0-7695-1977-6 (2003) 145 - 154
[13] Tufte, G., Haddow, P. C.: Towards Development on a Silicon-based Cellular. Computing Machine, Natural Computing. Vol. 4, Issue 4 (2005) 387 - 416
[14] Xilinx: Virtex 2.5V FPGA Detailed Functional Description. Version 2.8.1 (2002)
[15] Bäck, T., Hoffmeister, F., Schwefel, H. P.: A survey of evolutionary strategies. In R. Belew and L. Booker, editors, Proc. of the 4th International Conference on Genetic Algorithms, San Francisco, CA, 1991. Morgan Kaufmann (1991) 2 - 9
[16] Schwefel, H. P.: Numerical Optimization of Computer Models. John Wiley & Sons, Chichester, UK (1981)
[17] Miller, J.: An Empirical Study of the Efficiency of Learning Boolean Functions Using a Cartesian Genetic Programming Approach. In Proc. of the Genetic and Evolutionary Computation Conference. Volume 1, Orlando, USA (1999) 1135 - 1142
[18] Kalganova, T., Miller, J.: Evolving More Efficient Digital Circuits by Allowing Circuit Layout Evolution and Multi-objective Fitness. Proc. of the First NASA/DoD Conf. on Evolvable Hardware, IEEE Computer Society (1999) 54 - 63
[19] Kalganova, T.: Evolvable Hardware Design for Combinational Logic Circuits. PhD thesis, School of Computing, Napier University, Edinburgh, UK (2000)
[20] Xilinx: Virtex-E 1.8V FPGA Detailed Functional Description. Version 2.8 (2006)
[21] Xilinx: Virtex-II Complete Data Sheet. Version 3.4 (2005)
[22] Xilinx: Virtex-4 Data Sheet: DC and Switching Characteristics. Version 2.12 (2006)
[23] Lambert, C., Kalganova, T., Stomeo, E.: FPGA-based Systems for Evolvable Hardware. ICCS'06 Vienna, Austria, Volume 12, ISBN 975- 00803-1-9 (2006)