%0 Journal Article
	%A Md. Asif Jahangir Chowdhury and  Md. Shahriar Rizwan and  M. S. Islam
	%D 2012
	%J International Journal of Electrical and Computer Engineering
	%B World Academy of Science, Engineering and Technology
	%I Open Science Index 64, 2012
	%T An Efficient VLSI Design Approach to Reduce Static Power using Variable Body Biasing
	%U https://publications.waset.org/pdf/8289
	%V 64
	%X In CMOS integrated circuit design there is a trade-off between static power consumption and technology scaling. Recently, the power density has increased due to combination of higher clock speeds, greater functional integration, and smaller process geometries. As a result static power consumption is becoming more dominant. This is a challenge for the circuit designers. However, the designers do have a few methods which they can use to reduce this static power consumption. But all of these methods have some drawbacks. In order to achieve lower static power consumption, one has to sacrifice design area and circuit performance. In this paper, we propose a new method to reduce static power in the CMOS VLSI circuit using Variable Body Biasing technique without being penalized in area requirement and circuit performance.

	%P 452 - 456