%0 Journal Article
	%A Shipra Upadhyay  and  R. K. Nagaria and  R. A. Mishra
	%D 2012
	%J International Journal of Electronics and Communication Engineering
	%B World Academy of Science, Engineering and Technology
	%I Open Science Index 66, 2012
	%T Complementary Energy Path Adiabatic Logic based Full Adder Circuit
	%U https://publications.waset.org/pdf/7567
	%V 66
	%X In this paper, we present the design and experimental
evaluation of complementary energy path adiabatic logic (CEPAL)
based 1 bit full adder circuit. A simulative investigation on the
proposed full adder has been done using VIRTUOSO SPECTRE
simulator of cadence in 0.18μm UMC technology and its
performance has been compared with the conventional CMOS full
adder circuit. The CEPAL based full adder circuit exhibits the energy
saving of 70% to the conventional CMOS full adder circuit, at 100
MHz frequency and 1.8V operating voltage.
	%P 542 - 547