%0 Journal Article
	%A Kar Foo Chong and  Andreas Lee Astuti and  Pradeep K. Gopalakrishnan and  T. Hui Teo
	%D 2008
	%J International Journal of Electronics and Communication Engineering
	%B World Academy of Science, Engineering and Technology
	%I Open Science Index 18, 2008
	%T Digital Power Management Hardware Realization Using FPGA
	%U https://publications.waset.org/pdf/6883
	%V 18
	%X This paper describes design of a digital feedback loop
for a low switching frequency dc-dc switching converters. Low
switching frequencies were selected in this design. A look up table
for the digital PID (proportional integrator differentiator)
compensator was implemented using Altera Stratix II with built-in
ADC (analog-to-digital converter) to achieve this hardware
realization. Design guidelines are given for the PID compensator,
high frequency DPWM (digital pulse width modulator) and moving
average filter.
	%P 1155 - 1158