@article{(Open Science Index):https://publications.waset.org/pdf/6553,
	  title     = {Dual-Link Hierarchical Cluster-Based Interconnect Architecture for 3D Network on Chip},
	  author    = {Guang Sun and  Yong Li and  Yuanyuan Zhang and  Shijun Lin and  Li Su and  Depeng Jin and  Lieguang zeng},
	  country	= {},
	  institution	= {},
	  abstract     = {Network on Chip (NoC) has emerged as a promising
on chip communication infrastructure. Three Dimensional Integrate
Circuit (3D IC) provides small interconnection length between layers
and the interconnect scalability in the third dimension, which can
further improve the performance of NoC. Therefore, in this paper,
a hierarchical cluster-based interconnect architecture is merged with
the 3D IC. This interconnect architecture significantly reduces the
number of long wires. Since this architecture only has approximately
a quarter of routers in 3D mesh-based architecture, the average
number of hops is smaller, which leads to lower latency and higher
throughput. Moreover, smaller number of routers decreases the area
overhead. Meanwhile, some dual links are inserted into the bottlenecks
of communication to improve the performance of NoC.
Simulation results demonstrate our theoretical analysis and show the
advantages of our proposed architecture in latency, throughput and
area, when compared with 3D mesh-based architecture.},
	    journal   = {International Journal of Electronics and Communication Engineering},
	  volume    = {4},
	  number    = {9},
	  year      = {2010},
	  pages     = {1388 - 1392},
	  ee        = {https://publications.waset.org/pdf/6553},
	  url   	= {https://publications.waset.org/vol/45},
	  bibsource = {https://publications.waset.org/},
	  issn  	= {eISSN: 1307-6892},
	  publisher = {World Academy of Science, Engineering and Technology},
	  index 	= {Open Science Index 45, 2010},
	}