%0 Journal Article %A H. Loukil and A. Ben Atitallah and F. Ghozzi and M. A. Ben Ayed and N. Masmoudi %D 2008 %J International Journal of Electrical and Computer Engineering %B World Academy of Science, Engineering and Technology %I Open Science Index 22, 2008 %T A Pipelined FSBM Hardware Architecture for HTDV-H.26x %U https://publications.waset.org/pdf/5890 %V 22 %X In MPEG and H.26x standards, to eliminate the temporal redundancy we use motion estimation. Given that the motion estimation stage is very complex in terms of computational effort, a hardware implementation on a re-configurable circuit is crucial for the requirements of different real time multimedia applications. In this paper, we present hardware architecture for motion estimation based on "Full Search Block Matching" (FSBM) algorithm. This architecture presents minimum latency, maximum throughput, full utilization of hardware resources such as embedded memory blocks, and combining both pipelining and parallel processing techniques. Our design is described in VHDL language, verified by simulation and implemented in a Stratix II EP2S130F1020C4 FPGA circuit. The experiment result show that the optimum operating clock frequency of the proposed design is 89MHz which achieves 160M pixels/sec. %P 2287 - 2294