%0 Journal Article
	%A Ashwani K. Rana and  Narottam Chand and  Vinod Kapoor
	%D 2011
	%J International Journal of Electronics and Communication Engineering
	%B World Academy of Science, Engineering and Technology
	%I Open Science Index 58, 2011
	%T A Novel Source/Drain-to-Gate Non-overlap MOSFET to Reduce Gate Leakage Current in Nano Regime
	%U https://publications.waset.org/pdf/3314
	%V 58
	%X In this paper, gate leakage current has been mitigated
by the use of novel nanoscale MOSFET with Source/Drain-to-Gate
Non-overlapped and high-k spacer structure for the first time. A
compact analytical model has been developed to study the gate
leakage behaviour of proposed MOSFET structure. The result
obtained has found good agreement with the Sentaurus Simulation.
Fringing gate electric field through the dielectric spacer induces
inversion layer in the non-overlap region to act as extended S/D
region. It is found that optimal Source/Drain-to-Gate Non-overlapped
and high-k spacer structure has reduced the gate leakage current to
great extent as compared to those of an overlapped structure. Further,
the proposed structure had improved off current, subthreshold slope
and DIBL characteristic. It is concluded that this structure solves the
problem of high leakage current without introducing the extra series
resistance.
	%P 1132 - 1138