%0 Journal Article %A Arash Azizi Mazreah and Mohammad Reza Sahebi and Mohammad T. Manzuri Shalmani %D 2010 %J International Journal of Electronics and Communication Engineering %B World Academy of Science, Engineering and Technology %I Open Science Index 41, 2010 %T A Novel Nano-Scaled SRAM Cell %U https://publications.waset.org/pdf/15296 %V 41 %X To help overcome limits to the density of conventional SRAMs and leakage current of SRAM cell in nanoscaled CMOS technology, we have developed a four-transistor SRAM cell. The newly developed CMOS four-transistor SRAM cell uses one word-line and one bit-line during read/write operation. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 19% smaller than a conventional six-transistor cell using same design rules. Also the leakage current of new cell is 60% smaller than a conventional sixtransistor SRAM cell. Simulation result in 65nm CMOS technology shows new cell has correct operation during read/write operation and idle mode. %P 781 - 783