@article{(Open Science Index):https://publications.waset.org/pdf/15168,
	  title     = {Optimized Multiplier Based upon 6-Input Luts and Vedic Mathematics},
	  author    = {Zulhelmi Zakaria and  Shuja A. Abbasi},
	  country	= {},
	  institution	= {},
	  abstract     = {A new approach has been used for optimized design of multipliers based upon the concepts of Vedic mathematics. The design has been targeted to state-of-the art field-programmable gate arrays (FPGAs). The multiplier generates partial products using Vedic mathematics method by employing basic 4x4 multipliers designed by exploiting 6-input LUTs and multiplexers in the same slices resulting in drastic reduction in area. The multiplier is realized on Xilinx FPGAs using devices Virtex-5 and Virtex-6.Carry Chain Adder was employed to obtain final products. The performance of the proposed multiplier was examined and compared to well-known multipliers such as Booth, Carry Save, Carry ripple, and array multipliers. It is demonstrated that the proposed multiplier is superior in terms of speed as well as power consumption.
},
	    journal   = {International Journal of Electronics and Communication Engineering},
	  volume    = {7},
	  number    = {1},
	  year      = {2013},
	  pages     = {26 - 30},
	  ee        = {https://publications.waset.org/pdf/15168},
	  url   	= {https://publications.waset.org/vol/73},
	  bibsource = {https://publications.waset.org/},
	  issn  	= {eISSN: 1307-6892},
	  publisher = {World Academy of Science, Engineering and Technology},
	  index 	= {Open Science Index 73, 2013},
	}