%0 Journal Article
	%A Ki-Jin Kim and  Sanghoon Park and  K. H. Ahn
	%D 2012
	%J International Journal of Electronics and Communication Engineering
	%B World Academy of Science, Engineering and Technology
	%I Open Science Index 72, 2012
	%T 20 GHz Fractional Phased Locked Loop Circuit for the Gbps Wireless Communication
	%U https://publications.waset.org/pdf/15104
	%V 72
	%X This paper presents the 20-GHz fractional PLL (Phase
Locked Loop) circuit for the next generation Wi-Fi by using 90 nm
TSMC process. The newly suggested millimeter wave 16/17
pre-scalar is designed and verified by measurement to make the
fractional PLL having a low quantization noise. The operational
bandwidth of the 60 GHz system is 15 % of the carrier frequency
which requires large value of Kv (VCO control gain) resulting in
degradation of phase noise. To solve this problem, this paper adopts
AFC (Automatic Frequency Controller) controlled 4-bit millimeter
wave VCO with small value of Kv. Also constant Kv is implemented
using 4-bit varactor bank. The measured operational bandwidth is 18.2
~ 23.2 GHz which is 25 % of the carrier frequency. The phase noise of
-58 and -96.2 dBc/Hz at 100 KHz and 1 MHz offset is measured
respectively. The total power consumption of the PLL is only 30 mW.
	%P 1443 - 1446