%0 Journal Article
	%A Imron Rosyadi and  Ridha A. Djemal and  Saleh A. Alshebeili
	%D 2010
	%J International Journal of Electronics and Communication Engineering
	%B World Academy of Science, Engineering and Technology
	%I Open Science Index 38, 2010
	%T Design and Implementation of Real-Time Automatic Censoring System on Chip for Radar Detection
	%U https://publications.waset.org/pdf/14878
	%V 38
	%X Design and implementation of a novel B-ACOSD CFAR algorithm is presented in this paper. It is proposed for detecting radar target in log-normal distribution environment. The BACOSD detector is capable to detect automatically the number interference target in the reference cells and detect the real target by an adaptive threshold. The detector is implemented as a System on Chip on FPGA Altera Stratix II using parallelism and pipelining technique. For a reference window of length 16 cells, the experimental results showed that the processor works properly with a processing speed up to 115.13MHz and processing time0.29 ┬Ás, thus meets real-time requirement for a typical radar system.

	%P 275 - 281