@article{(Open Science Index):https://publications.waset.org/pdf/14759,
	  title     = {Improved Modulo 2n +1 Adder Design},
	  author    = {Somayeh Timarchi and  Keivan Navi},
	  country	= {},
	  institution	= {},
	  abstract     = {Efficient modulo 2n+1 adders are important for
several applications including residue number system, digital signal
processors and cryptography algorithms. In this paper we present a
novel modulo 2n+1 addition algorithm for a recently represented
number system. The proposed approach is introduced for the
reduction of the power dissipated. In a conventional modulo 2n+1
adder, all operands have (n+1)-bit length. To avoid using (n+1)-bit
circuits, the diminished-1 and carry save diminished-1 number
systems can be effectively used in applications. In the paper, we also
derive two new architectures for designing modulo 2n+1 adder, based
on n-bit ripple-carry adder. The first architecture is a faster design
whereas the second one uses less hardware. In the proposed method,
the special treatment required for zero operands in Diminished-1
number system is removed. In the fastest modulo 2n+1 adders in
normal binary system, there are 3-operand adders. This problem is
also resolved in this paper. The proposed architectures are compared
with some efficient adders based on ripple-carry adder and highspeed
adder. It is shown that the hardware overhead and power
consumption will be reduced. As well as power reduction, in some
cases, power-delay product will be also reduced.},
	    journal   = {International Journal of Electrical and Computer Engineering},
	  volume    = {2},
	  number    = {3},
	  year      = {2008},
	  pages     = {472 - 479},
	  ee        = {https://publications.waset.org/pdf/14759},
	  url   	= {https://publications.waset.org/vol/15},
	  bibsource = {https://publications.waset.org/},
	  issn  	= {eISSN: 1307-6892},
	  publisher = {World Academy of Science, Engineering and Technology},
	  index 	= {Open Science Index 15, 2008},
	}