Efficient Hardware Architecture of the Direct 2- D Transform for the HEVC Standard
Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 32769
Efficient Hardware Architecture of the Direct 2- D Transform for the HEVC Standard

Authors: Fatma Belghith, Hassen Loukil, Nouri Masmoudi

Abstract:

This paper presents the hardware design of a unified architecture to compute the 4x4, 8x8 and 16x16 efficient twodimensional (2-D) transform for the HEVC standard. This architecture is based on fast integer transform algorithms. It is designed only with adders and shifts in order to reduce the hardware cost significantly. The goal is to ensure the maximum circuit reuse during the computing while saving 40% for the number of operations. The architecture is developed using FIFOs to compute the second dimension. The proposed hardware was implemented in VHDL. The VHDL RTL code works at 240 MHZ in an Altera Stratix III FPGA. The number of cycles in this architecture varies from 33 in 4-point- 2D-DCT to 172 when the 16-point-2D-DCT is computed. Results show frequency improvements reaching 96% when compared to an architecture described as the direct transcription of the algorithm.

Keywords: HEVC, Modified Integer Transform, FPGA.

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1083161

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2688

References:


[1] Gary J.Sullivan, Pankaj Topiwala, and Ajay Luthra, "The H.264/AVC Advanced Video Coding Standard:Overview and Introduction to the Fidelity Range Extensions" SPIE Conference on Applications of Digital Image Processing XXVII. Special Session on Advances in the New Emerging Standard: H.264/AVC, August, 2004.
[2] Gary J. Sullivan and Jens-Rainer Ohm "Recent developments in standardization of high efficiency video coding (HEVC)". SPIE Conference on Applications of Digital Image Processing XXVII. Proceeding of SPIE Volume 7798, August,2010.
[3] Gary J.Sullivan, Jens-Rainer Ohm, Woo-Jin Han, "Overview of the High Efficiency Video Coding (HEVC) standard" IEE Trans. On Circuits and Systems for Video Technology, December 2012.
[4] Ashfaq Ahmed, Muhammad Awais, Martina Maurizio and Guido Masera "VLSI Implementation of 16-point DCT for H.265/HEVC using Walsh Hadamard Transform and Lifting Scheme". IEEE 14th International Multitopic Conference. December 2011.
[5] Ricardo Jeske, José Cl├íudio de Souza Jr., Gustavo Wrege, Ruhan Concei├º├úo, Mateus Grellert, J├║lio Mattos and Luciano Agostini "Low Cost and High Throughput Multiplierless Design of a 16 Point 1-D DCT of the New HEVC Video Coding Standard" VIII Southern Programmable Logic Conference (SPL), March 2012.
[6] Muhammad Martuza and Khan A.Wahid "Low Cost Design of a Hybrid Architecture of Integer Inverse DCT for H.264, VC-1, AVS, and HEVC" Hindawi Publishing Corporation ,VLSI Design,Volume 2012.
[7] Jong-Sik Park, Woo-Jin Nam, Seung-Mok Han, and Seongsoo Lee. "2- D Large Inverse Transform (16x16, 32x32) for HEVC (High Efficiency Video Coding)" Journal of Semiconductor Technology and Science, vol.12, June 2012.
[8] Benjamin Bross, Woo-Jin Han Jens Rainer Ohm and Gary J.Sullivan "JCT-VC-G1103 Working Draft 5 WD 5", Novembre 2011.
[9] Fatma Belghith, Hassen Loukil and Nouri Masmoudi "Free Multiplication integer Transformation for the HEVC Standard" The 10th International Multi-Conference on Systems, Signals and Devices (SSD) March 2013, in press .
[10] Antonio J. D├¡az-Honrubia, José Luis Mart├¡nez and Pedro Cuenca, " HEVC:A Review, Trends and Challenges" 2nd Workshop on MultimediaData Coding and Transmission, September 2011.