TY - JFULL AU - Z. X. Chen and N. Singh and D.-L. Kwong PY - 2011/10/ TI - Vertical Silicon Nanowire MOSFET With A Fully-Silicided (FUSI) NiSi2 Gate T2 - International Journal of Electronics and Communication Engineering SP - 1228 EP - 1231 VL - 5 SN - 1307-6892 UR - https://publications.waset.org/pdf/14024 PU - World Academy of Science, Engineering and Technology NX - Open Science Index 57, 2011 N2 - This paper presents a vertical silicon nanowire n- MOSFET integrated with a CMOS-compatible fully-silicided (FUSI) NiSi2 gate. Devices with nanowire diameter of 50nm show good electrical performance (SS < 70mV/dec, DIBL < 30mV/V, Ion/Ioff > 107). Most significantly, threshold voltage tunability of about 0.2V is shown. Although threshold voltage remains low for the 50nm diameter device, it is expected to become more positive as nanowire diameter reduces. ER -