WASET

	%0 Journal Article
	%A Z. X. Chen and  N. Singh and  D.-L. Kwong
	%D 2011
	%J International Journal of Electronics and Communication Engineering
	%B World Academy of Science, Engineering and Technology
	%I Open Science Index 57, 2011
	%T Vertical Silicon Nanowire MOSFET With A Fully-Silicided (FUSI) NiSi2 Gate
	%U https://publications.waset.org/pdf/14024
	%V 57
	%X This paper presents a vertical silicon nanowire n- MOSFET integrated with a CMOS-compatible fully-silicided (FUSI) NiSi2 gate. Devices with nanowire diameter of 50nm show good electrical performance (SS &lt; 70mV/dec, DIBL &lt; 30mV/V, Ion/Ioff &gt; 107). Most significantly, threshold voltage tunability of about 0.2V is shown. Although threshold voltage remains low for the 50nm diameter device, it is expected to become more positive as nanowire diameter reduces.

	%P 1229 - 1231