@article{(Open Science Index):https://publications.waset.org/pdf/12643,
	  title     = {A 16Kb 10T-SRAM with 4x Read-Power Reduction},
	  author    = {Pardeep Singh and  Sanjay Sharma and  Parvinder S. Sandhu},
	  country	= {},
	  institution	= {},
	  abstract     = {This work aims to reduce the read power consumption
as well as to enhance the stability of the SRAM cell during the read
operation. A new 10-transisor cell is proposed with a new read
scheme to minimize the power consumption within the memory core.
It has separate read and write ports, thus cell read stability is
significantly improved. A 16Kb SRAM macro operating at 1V
supply voltage is demonstrated in 65 nm CMOS process. Its read
power consumption is reduced to 24% of the conventional design.
The new cell also has lower leakage current due to its special bit-line
pre-charge scheme. As a result, it is suitable for low-power mobile
applications where power supply is restricted by the battery.},
	    journal   = {International Journal of Electrical and Computer Engineering},
	  volume    = {5},
	  number    = {1},
	  year      = {2011},
	  pages     = {97 - 101},
	  ee        = {https://publications.waset.org/pdf/12643},
	  url   	= {https://publications.waset.org/vol/49},
	  bibsource = {https://publications.waset.org/},
	  issn  	= {eISSN: 1307-6892},
	  publisher = {World Academy of Science, Engineering and Technology},
	  index 	= {Open Science Index 49, 2011},
	}