Padmanabhan Balasubramanian and  Karthik Anantha,  Power and Delay Optimized Graph Representation for Combinational Logic Circuits.   journal   = {International Journal of Structural and Construction Engineering}, [online]. World Academy of Science, Engineering and Technology.
    August 2007, vol. 8(8). 2481 - 2487
    [viewed 23 April 2024]. Available from: https://publications.waset.org/pdf/11738.