%0 Journal Article
	%A S. Heydarzadeh and  A. Kadivarian and  P. Torkzadeh
	%D 2012
	%J International Journal of Electronics and Communication Engineering
	%B World Academy of Science, Engineering and Technology
	%I Open Science Index 69, 2012
	%T Implemented 5-bit 125-MS/s Successive Approximation Register ADC on FPGA
	%U https://publications.waset.org/pdf/10748
	%V 69
	%X Implemented 5-bit 125-MS/s successive
approximation register (SAR) analog to digital converter (ADC) on
FPGA is presented in this paper.The design and modeling of a high
performance SAR analog to digital converter are based on monotonic
capacitor switching procedure algorithm .Spartan 3 FPGA is chosen
for implementing SAR analog to digital converter algorithm. SAR
VHDL program writes in Xilinx and modelsim uses for showing
results.
	%P 927 - 930