@article{(Open Science Index):https://publications.waset.org/pdf/10748,
	  title     = {Implemented 5-bit 125-MS/s Successive Approximation Register ADC on FPGA},
	  author    = {S. Heydarzadeh and  A. Kadivarian and  P. Torkzadeh},
	  country	= {},
	  institution	= {},
	  abstract     = {Implemented 5-bit 125-MS/s successive
approximation register (SAR) analog to digital converter (ADC) on
FPGA is presented in this paper.The design and modeling of a high
performance SAR analog to digital converter are based on monotonic
capacitor switching procedure algorithm .Spartan 3 FPGA is chosen
for implementing SAR analog to digital converter algorithm. SAR
VHDL program writes in Xilinx and modelsim uses for showing
results.},
	    journal   = {International Journal of Electronics and Communication Engineering},
	  volume    = {6},
	  number    = {9},
	  year      = {2012},
	  pages     = {927 - 930},
	  ee        = {https://publications.waset.org/pdf/10748},
	  url   	= {https://publications.waset.org/vol/69},
	  bibsource = {https://publications.waset.org/},
	  issn  	= {eISSN: 1307-6892},
	  publisher = {World Academy of Science, Engineering and Technology},
	  index 	= {Open Science Index 69, 2012},
	}