A Reversible CMOS AD / DA Converter Implemented with Pseudo Floating-Gate
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A Reversible CMOS AD / DA Converter Implemented with Pseudo Floating-Gate

Authors: Omid Mirmotahari, Yngvar Berg, Ahmad Habibizad Navin

Abstract:

Reversible logic is becoming more and more prominent as the technology sets higher demands on heat, power, scaling and stability. Reversible gates are able at any time to "undo" the current step or function. Multiple-valued logic has the advantage of transporting and evaluating higher bits each clock cycle than binary. Moreover, we demonstrate in this paper, combining these disciplines we can construct powerful multiple-valued reversible logic structures. In this paper a reversible block implemented by pseudo floatinggate can perform AD-function and a DA-function as its reverse application.

Keywords: Reversible logic, bi-directional, Pseudo floating-gate(PFG), multiple-valued logic (MVL).

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1075761

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References:


[1] R. Landauer. "Irreversibility and Heat Generation in the Computing Process". IBM Journal of Research and Development, 5(3):183-191, July 1961.
[2] C.H. Bennett and R. Landauer. "The Fundamental Physical Limits of Computation". Scientific American, 253(1):38-46, July 1985.
[3] K.C. Smith. "Multiple-Valued logic: a tutorial and appreciation". IEEE Computers, 21:17-27, April 1988.
[4] D. Etiemble. "On the performance of the Multiple-Valued integrated Circuits: Past, Present and Future". Proceeding 22nd IEEE International Symposia on Multiple-Valued Logic (ISMVL), pages 154-164, May 1992.
[5] T. Shibata and T. Ohmi. "A Functional MOS Transistor Featuring Gate- Level Weighted Sum and Threshold Operations". IEEE Transactions on Electron Devices, 39(6):1444-1455, June 1992.
[6] C. Diorio, S. Mahajan, P. Hasler, B. Minch and C. Mead. "A High- Resolution Non-Volatile Analog Memory Cell". Proc. IEEE Intl. Symp. on Circuits and Systems, 3:2233-2236, 1995.
[7] Y. Berg, T. S. Lande and Ø. Næss. "Programming Floating-Gate Circuits with UV-Activated Condictances". IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 48(1):12-19, January 2001.
[8] Y. Berg, S. Aunet, O. Mirmotahari and M. H├©vin. "Novel Recharged Semi-Floating-Gate CMOS Logic for Multiple-Valued Systems". IEEE International Symposium on Circuits and Systems (ISCAS), 5:193-196, May 2003.
[9] K. Kotani, T. Shibata, M. Imai and T. Ohmi. "Clocked-Neuron- MOS Logic Circuits Employing Auto-Threshold-Adjustment". IEEE International Solid-State Circuits Conference (ISSCC), 388:320-321, February 1995.
[10] O. Mirmotahari, J. Lomsdalen and Y. Berg. "A Continuous Mode MVL Gate using Pseudo Floating-Gate". 14th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES), pages 185- 189, June 2007.
[11] Y. Berg, O. Mirmotahari and S. Aunet. "Pseudo Floating-Gate Inverter With Feedback Control". IFIP International Conference on Very Large Scale Integration (VLSI-SOC), 1:272-276, October 2006.
[12] O. Mirmotahari, Y. Berg, J. Lomsdalen and V. ├ÿver┬░as. "Using Multiple- Valued Gates to Implement Reversible Logic". Ph.D. Research in Microelectronics and Electronics (PRIME), 1:361-364, June 2006.