%0 Journal Article
	%A Muhammad Ali and  Awais Adnan
	%D 2008
	%J International Journal of Computer and Information Engineering
	%B World Academy of Science, Engineering and Technology
	%I Open Science Index 19, 2008
	%T Comparative Analysis of Transient-Fault Tolerant Schemes for Network on Chips
	%U https://publications.waset.org/pdf/10695
	%V 19
	%X Network on a chip (NoC) has been proposed as a viable solution to counter the inefficiency of buses in the current VLSI on-chip interconnects. However, as the silicon chip accommodates more transistors, the probability of transient faults is increasing, making fault tolerance a key concern in scaling chips. In packet based communication on a chip, transient failures can corrupt the data packet and hence, undermine the accuracy of data communication. In this paper, we present a comparative analysis of transient fault tolerant techniques including end-to-end, node-by-node, and stochastic communication based on flooding principle.

	%P 2348 - 2353