Reversible Signed Division for Computing Systems
Applications of reversible logic gates in the design of complex integrated circuits provide power optimization. This technique finds a great use in low power CMOS design, optical computing, quantum computing and nanotechnology. This paper proposes a reversible signed division circuit that can divide an n-bit signed dividend with an n-bit signed divisor using non-restoration division logic. The proposed design adequately addresses the ‘delay’ there by improving the efficiency of the circuit. An attempt is made to design a reversible signed division circuit. This paper provides a threshold to build more complex arithmetic systems using reversible logic, thus increasing the performance of computing systems.
Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1316812Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 357
 R. Landauer, “Irreversibility and Heat Generation in the Computing Process”, IBM J. Research and Development, vol. 3, pp. 183-191, July 1961.
 C. H. Bennett, “Logical Reversibility of Computation”, IBM J. Research and Development, pp.525-532, November 1973.
 Thapliyal, H. and Ranganathan, N., “Design of Reversible Sequential Circuits optimizing Quantum Cost, Delay, and Garbage Outputs”, 2010 ACM J. Emerg. Technol. Comput. Syst. 6, 4, Article 14, (December 2010), 31 pages.
 D. Krishnaveni, M. Geetha Priya,‘A Novel Design of Reversible Serial and Parallel Adder/ Subtractor’ IJEST vol 3,No 3, March 2011, pg 2280-2288.
 D. Krishnaveni, M. Geetha Priya, K. Baskaran, “Design of an Efficient Reversible 8x8 Wallace Tree Multiplier” World Applied Sciences Journal 20 (8): 1159-1165, © IDOSI Publications, 2012
 H.R.Bhagyalakshmi and M.K.Venkatesha, ‘An improved design of a multiplier using reversible logic gates’, International Journal of Engineering Science and Technology Vol. 2(8), 2010, 3838-3845
 D. Krishnaveni, M. Geetha Priya,‘A Novel Reversible EX-NOR SV Gate and Its Application’ vol 5, LNNS series, Springer, pg 105-114. Net
 Carl Hamacher, Zvonko Vranesic, Safwat Zaky, Computer Organization, 3rd Edition, McGraw-Hill, New York, 2002.
 D. Krishnaveni, M. Geetha Priya, “A Novel Design of Reversible Universal Shift Register with Reduced Delay and Quantum Cost”, Journal of Comuting, Volume 4, Issue 2, February 2012
 D. Krishnaveni, M. Geetha Priya, “A Novel Reversible n–Bit Counter for Low Power Quantum Computing”, International Journal of Control Theory and Applications, Vol.No.10, Issue No.3, 2017, Pg 11-20.