%0 Journal Article
	%A Shashank Gautam and  Pramod Sharma
	%D 2016
	%J International Journal of Electronics and Communication Engineering
	%B World Academy of Science, Engineering and Technology
	%I Open Science Index 119, 2016
	%T An Improved Design of Area Efficient Two Bit Comparator
	%U https://publications.waset.org/pdf/10006143
	%V 119
	%X In present era, development of digital circuits, signal processors and other integrated circuits, magnitude comparators are challenged by large area and more power consumption. Comparator is most basic circuit that performs comparison. This paper presents a technique to design a two bit comparator which consumes less area and power. DSCH and MICROWIND version 3 are used to design the schematic and design the layout of the schematic, observe the performance parameters at different nanometer technologies respectively.

	%P 1409 - 1415