%0 Journal Article
	%A Vinod Kumar Khera and  R. K. Sharma and  A. K. Gupta
	%D 2016
	%J International Journal of Electronics and Communication Engineering
	%B World Academy of Science, Engineering and Technology
	%I Open Science Index 109, 2016
	%T Reducing Test Vectors Count Using Fault Based Optimization Schemes in VLSI Testing
	%U https://publications.waset.org/pdf/10005719
	%V 109
	%X Power dissipation increases exponentially during test mode as compared to normal operation of the circuit. In extreme cases, test power is more than twice the power consumed during normal operation mode. Test vector generation scheme is key component in deciding the power hungriness of a circuit during testing. Test vector count and consequent leakage current are functions of test vector generation scheme. Fault based test vector count optimization has been presented in this work. It helps in reducing test vector count and the leakage current. In the presented scheme, test vectors have been reduced by extracting essential child vectors. The scheme has been tested experimentally using stuck at fault models and results ensure the reduction in test vector count.
	%P 176 - 179