TY - JFULL AU - Shobha Sharma and Amita Dev and Akanksha Kant PY - 2016/3/ TI - An Efficient Implementation of High Speed Vedic Multiplier Using Compressors for Image Processing Applications T2 - International Journal of Computer and Information Engineering SP - 389 EP - 395 VL - 10 SN - 1307-6892 UR - https://publications.waset.org/pdf/10004068 PU - World Academy of Science, Engineering and Technology NX - Open Science Index 110, 2016 N2 - Digital signal processor, image signal processor and FIR filters have multipliers as an important part of their design. On the basis of Vedic mathematics, Vedic multipliers have come out to be very fast multipliers. One of the image processing applications is edge detection. This research presents a small area and high speed 8 bit Vedic multiplier system comprising of compressor based adders. This results in faster edge detection. This architecture is tested on Xilinx vertex 4 FPGA board and simulations were carried out using the Xilinx synthesis tool. Comparisons are made and this system is found to be smaller in area with high speed (the lesser propagation delay). This compressor based Vedic multiplier is 1.1 times speedier than a typical Vedic multiplier. Also, this Vedic Multiplier is 2 times speedier than a ‘simple’ multiplier. ER -