%0 Journal Article %A Abdelmonaem Ayachi and Belgacem Hamdi %D 2016 %J International Journal of Electronics and Communication Engineering %B World Academy of Science, Engineering and Technology %I Open Science Index 109, 2016 %T A Fault-Tolerant Full Adder in Double Pass CMOS Transistor %U https://publications.waset.org/pdf/10003320 %V 109 %X This paper presents a fault-tolerant implementation for adder schemes using the dual duplication code. To prove the efficiency of the proposed method, the circuit is simulated in double pass transistor CMOS 32nm technology and some transient faults are voluntary injected in the Layout of the circuit. This fully differential implementation requires only 20 transistors which mean that the proposed design involves 28.57% saving in transistor count compared to standard CMOS technology. %P 36 - 40