Highly Optimized Novel High Speed Low Power Barrel Shifter at 22nm Hi K Metal Gate Strained Si Technology Node
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Highly Optimized Novel High Speed Low Power Barrel Shifter at 22nm Hi K Metal Gate Strained Si Technology Node

Authors: Shobha Sharma, Amita Dev

Abstract:

This research paper presents highly optimized barrel shifter at 22nm Hi K metal gate strained Si technology node. This barrel shifter is having a unique combination of static and dynamic body bias which gives lowest power delay product. This power delay product is compared with the same circuit at same technology node with static forward biasing at ‘supply/2’ and also with normal reverse substrate biasing and still found to be the lowest. The power delay product of this barrel sifter is .39362X10-17J and is lowered by approximately 78% to reference proposed barrel shifter at 32nm bulk CMOS technology. Power delay product of barrel shifter at 22nm Hi K Metal gate technology with normal reverse substrate bias is 2.97186933X10-17J and can be compared with this design’s PDP of .39362X10-17J. This design uses both static and dynamic substrate biasing and also has approximately 96% lower power delay product compared to only forward body biased at half of supply voltage. The NMOS model used are predictive technology models of Arizona state university and the simulations to be carried out using HSPICE simulator.

Keywords: Dynamic body biasing, highly optimized barrel shifter, PDP, Static body biasing.

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1338299

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References:


[1] H.Solemon, K Roy et al, ’Robust subthreshold logic for ultra low power operations’, ieee tran. VLSI system,vol9,p90-99, 2001
[2] John F Wakerly,” digital design principles and practices”, 4th edition, July31, 2005.
[3] Abhijit Asti et al,” A purely MUX based high speed shifter VLSI implementation using three different logic design styles”, International conference of Mechanical engineering and Technology, Springer, ASIC 125 pp 639-646, 2012.
[4] Renu Pappachan et al, “Design and analysis of a 4 bit low power barrel shifter in 20nm finfet technology” IJES pp17-25, 2013.
[5] K Dang and Anderson, “High Speed barrel shifter” US Patent 5,416731, may 1995
[6] A Yamaguchi, ”bidirectional shifter” US Patent 5,262971, November 1993
[7] M Seckora, ”barrel shifter or multiply/divide IC structure, ”US Patent 5,465222, November1995
[8] M. diamond Stein and H Srinivas,”Fast conversion two’s complement encoded shift value for a barrel shifter,” US Patent 5,948,050, september1999.