%0 Journal Article
	%A Shashank Gautam
	%D 2015
	%J International Journal of Electronics and Communication Engineering
	%B World Academy of Science, Engineering and Technology
	%I Open Science Index 100, 2015
	%T Designing of Full Adder Using Low Power Techniques
	%U https://publications.waset.org/pdf/10001367
	%V 100
	%X This paper proposes techniques like MT CMOS,
POWER GATING, DUAL STACK, GALEOR and LECTOR to
reduce the leakage power. A Full Adder has been designed using
these techniques and power dissipation is calculated and is compared
with general CMOS logic of Full Adder.
Simulation results show the validity of the proposed techniques is
effective to save power dissipation and to increase the speed of
operation of the circuits to a large extent.

	%P 983 - 987