WASET
    Sunil Jadav and  Rajeevan Chandel Munish Vashishath,  A Superior Delay Estimation Model for VLSI Interconnect in Current Mode Signaling.   journal   = {International Journal of Electronics and Communication Engineering}, [online]. World Academy of Science, Engineering and Technology.
    March 2015, vol. 98(2). 492 - 497
    [viewed 20 April 2024]. Available from: https://publications.waset.org/pdf/10001108.